Todd E. Leonard

Three-dimensional inter-chip contact through vertical displacement MEMS

Aligning FIFO pointers in a data communications lane of a serial link

Three-dimensional chip stack for self-powered integrated circuit

Adaptable receiver detection

Three-dimensional inter-chip contact through vertical displacement MEMS

Source series terminated driver circuit with programmable output resistance, amplitude reduction, and equalization

Critical path redundant logic for mitigation of hardware across chip variation

System-on-chip (SOC), design structure and method

System-on-chip (SOC), design structure and method

WARRANTY MONITORING AND ENFORCEMENT FOR INTEGRATED CIRCUIT

Warranty monitoring and enforcement for integrated circuit and related design structure

System and method for improving equalization in a high speed serdes environment

SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES ENVIRONMENT

Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs

STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT

UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT

DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM

On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations

Dynamic critical path detector for digital logic circuit paths

Dynamic critical path detector for digital logic circuit paths

Design structures of powering on integrated circuit

Method and systems of powering on integrated circuit

Design structures, method and systems of powering on integrated circuit

Method for monitoring BER in an infiniband environment

Method for monitoring channel eye characteristics in a high-speed SerDes data link

Executing Software Within Real-Time Hardware Constraints Using Functionally Programmable Branch Table

METHOD AND PROCESSING UNIT FOR INTER-CHIP COMMUNICATION

Structure for task based debugger (transaction-event-job-trigger)

Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs

Task based debugger (transaction-event-job-trigger)

Multilevel parallel CRC generation and checking circuit

Scalable cyclic redundancy check circuit