Inventor profile of:

Ping LU

City:

Cary, North Carolina

Country:

United States

Published Applications:

12

Last publication date:

2026-01-01

Top Assignees for applications by Ping LU

The entities that hold a legal rights for patent applications filed by inventor LU Ping:

Recent patent applications by LU Ping

Ping LU from Cary, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-01-01
US20260003386A1
Physics

SERIALIZED DATA LINK WITH ZERO-CYCLE OR SHORT-CYCLE PATHS

#2 | 2025-12-11
US20250378039A1
Physics

MULTI-DIE SYSTEMS WITH MODULAR DIE-TO-DIE LINK MACROS FOR ENABLING DIE-TO-DIE COMMUNICATION

#3 | 2025-05-22
US20250167776A1
Electricity

PHASE INTERPOLATOR (PI) INCLUDING WEIGHTED SUMMING CIRCUIT AND RELATED METHODS

#4 | 2025-05-08
US20250150253A1
Electricity

PHASE INTERPOLATOR (PI) WITH CLAMPING CIRCUIT TO LIMIT OPERATION TO RANGE HAVING OPTIMAL INTEGRAL NON-LINEARITY AND RELATED METHODS

#5 | 2025-05-08
US20250147468A1
Physics

TIME TO DIGITAL CONVERTER (TDC) CIRCUIT WITH SELF-ADAPTIVE TIME GRANULARITY AND RELATED METHODS

#6 | 2025-05-01
US20250141456A1
Electricity

DIGITAL PHASE-LOCKED LOOPS (PLL) INCLUDING CLOSED-LOOP TIME-TO-DIGITAL CONVERTER (TDC) GAIN CALIBRATION CIRCUITS AND RELATED METHODS

#7 | 2024-10-31
US20240361729A1
Physics

TIME-TO-DIGITAL CONVERTERS (TDC) EMPLOYING A SINGLE-STAGE DELAY PAIR AND NOISE SHAPING FOR WIDE INPUT RANGE AND REDUCED QUANTIZATION NOISE IN A PHASE-LOCKED LOOP (PLL)

#8 | 2024-08-29
US20240291495A1
Electricity

Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods

#9 | 2024-08-08
US20240267052A1
Electricity

PHASE-LOCKED LOOPS (PLL) INCLUDING DIGITALLY CONTROLLED OSCILLATOR (DCO) GAIN CALIBRATION CIRCUITS AND RELATED METHODS

#10 | 2024-02-29
US20240069074A1
Physics

Peak voltage amplitude detectors tolerant to process variation and device mismatch and related methods

#11 | 2023-11-30
US20230384738A1
Physics

Time to digital converter (TDC) circuit with self-adaptive time granularity and related methods

#12 | 2023-07-06
US20230216509A1
Electricity

Phase-locked-loop circuit employing a hybrid loop filter with sample and hold capacitors for reduced signal jitter, and related methods

InventorID:

5793940 ⎘