Schoenaich
Germany
44
2022-12-01
The entities that hold a legal rights for patent applications filed by inventor Gaertner Ute:
Ute Gaertner from Schoenaich, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Operating system deactivation of storage block write protection absent quiescing of processors
#2 | 2022-12-01Reset dynamic address translation protection instruction
#3 | 2019-09-19Suspending translation look-aside buffer purge execution in a multi-processor environment
#4 | 2019-08-22Zone-SDID mapping scheme for TLB purges
#5 | 2018-12-20Suspending translation look-aside buffer purge execution in a multi-processor environment
#6 | 2018-12-20Suspending translation look-aside buffer purge execution in a multi-processor environment
#7 | 2018-12-20Suspending translation look-aside buffer purge execution in a multi-processor environment
#8 | 2018-12-13Zone-SDID mapping scheme for TLB purges
#9 | 2018-12-13Zone-SDID mapping scheme for TLB purges
#10 | 2017-05-11Protecting a memory from unauthorized access
#11 | 2017-05-11Protecting a memory from unauthorized access
#12 | 2017-03-14Encrypted data exchange between computer systems
#13 | 2017-02-02Processing interrupt requests
#14 | 2017-02-02Data collection in a multi-threaded processor
#15 | 2017-02-02Processing interrupt requests
#16 | 2017-02-02DATA COLLECTION IN A MULTI-THREADED PROCESSOR
#17 | 2016-11-03Suppressing virtual address translation utilizing bits and instruction tagging
#18 | 2016-10-06Protecting storage from unauthorized access
#19 | 2016-10-06Protecting contents of storage
#20 | 2016-10-06Protecting contents of storage
#21 | 2016-10-06Protecting storage from unauthorized access
#22 | 2016-08-30Encrypted data exchange between computer systems
#23 | 2016-05-19Recovery improvement for quiesced systems
#24 | 2016-05-19Recovery improvement for quiesced systems
#25 | 2016-05-19Quiesce handling in multithreaded environments
#26 | 2016-05-19Quiesce handling in multithreaded environments
#27 | 2014-05-08Suppressing virtual address translation utilizing bits and instruction tagging
#28 | 2014-05-08Suppressing virtual address translation utilizing bits and instruction tagging
#29 | 2014-05-08Reducing microprocessor performance loss due to translation table coherency in a multi-processor system
#30 | 2014-05-08Reducing microprocessor performance loss due to translation table coherency in a multi-processor system
#31 | 2014-01-23Operating on translation look-aside buffers in a multiprocessor environment
#32 | 2013-12-19Monitoring a value in storage without repeated storage access
#33 | 2013-12-19Monitoring a value in storage without repeated storage access
#34 | 2012-06-07System, method and computer program product for providing a programmable quiesce filtering register
#35 | 2011-12-29Facilitating quiesce operations within a logically partitioned computer system
#36 | 2011-12-29Translating translation requests having associated priorities
#37 | 2009-08-27Providing multiple quiesce state machines in a computing environment
#38 | 2009-08-27System, method and computer program product for providing quiesce filtering for shared memory
#39 | 2009-08-27System, method and computer program product for providing a programmable quiesce filtering register
#40 | 2009-07-23Method for address translation in virtual machines
#41 | 2008-12-25Translation lookaside buffer and related method and program product utilized for virtual addresses
#42 | 2006-03-28Blocking processing restrictions based on page indices
#43 | 2006-02-07Blocking processing restrictions based on addresses
#44 | 2005-03-10Central processing unit having a module for processing of function calls
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