Brian D. Barrick

Fast mapper restore for flush in processor

Inferring future value for speculative branch resolution in a microprocessor

Assignment of microprocessor register tags at issue time

Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction

Dependency skipping execution

Inferring future value for speculative branch resolution

Execution elision of intermediate instruction by processor

Fast perfect issue of dependent instructions in a distributed issue queue system

Assignment of microprocessor register tags at issue time

Program counter (PC)-relative load and store addressing for fused instructions

On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer

Pairing issue queues for complex instructions and instruction fusion

Processor providing intelligent management of values buffered in overlaid architected and non-architected register files

Fusion to enhance early address generation of load instructions in a microprocessor

Check pointing of accumulator register results in a microprocessor

Logical register recovery within a processor

System and handling of register data in processors

System and handling of register data in processors

High bandwidth logical register flush recovery

Register file write using pointers

Supporting speculative microprocessor instruction execution

Slice-based allocation history buffer

Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor

Logical register recovery within a processor

Flush-recovery bandwidth in a processor

Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor

Multiple Level History Buffer for Transaction Memory Support

DYNAMIC ADJUSTMENT OF ISSUE-TO-ISSUE DELAY BETWEEN DEPENDENT INSTRUCTIONS

Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor

Cache miss thread balancing

Operation of a multi-slice processor implementing a hardware level transfer of an execution thread

Data-less history buffer with banked restore ports in a register mapper

Issue queue snooping for asynchronous flush and restore of distributed history buffer

Asynchronous flush and restore of distributed history buffer

Slice-based allocation history buffer

Simplified processor sparing

Multi-level history buffer for transaction memory in a microprocessor

Cache miss thread balancing

Operation of a multi-slice processor with selective producer instruction types

Operation of a multi-slice processor with selective producer instruction types

ECC scrubbing method in a multi-slice microprocessor

ECC scrubbing in a multi-slice microprocessor

Direct register restore mechanism for distributed history buffers

Merging status and control data in a reservation station

FPSCR STICKY BIT HANDLING FOR OUT OF ORDER INSTRUCTION EXECUTION

In-pipe error scrubbing within a processor core

Operation of a multi-slice processor implementing a hardware level transfer of an execution thread

Operation of a multi-slice processor with history buffers storing transaction memory state information

Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction

Operation of a multi-slice processor with selective producer instruction types

Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction

Operation of a multi-slice processor with reduced flush and restore latency

Operation of a multi-slice processor with selective producer instruction types

Operation of a multi-slice processor with reduced flush and restore latency

Managing a free list of resources to decrease control complexity and reduce power consumption

Managing a free list of resources to decrease control complexity and reduce power consumption

Managing a free list of resources to decrease control complexity and reduce power consumption

Register file mapping

Dynamic assignment across dispatch pipes of source ports to be used to obtain indication of physical registers

Freelist based global completion table having both thread-specific and global completion table identifiers

Freelist based global completion table having both thread-specific and global completion table identifiers

Store data forwarding with no memory model restrictions

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

SPECIAL CASE REGISTER UPDATE WITHOUT EXECUTION

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

Program status word dependency handling in an out of order microprocessor design

Intermediate register mapper

Dual-issuance of microprocessor instructions using dual dependency matrices

Method, system and computer program product for storing external device result data

Store data forwarding with no memory model restrictions

Specialized store queue and buffer design for silent store implementation

Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions

Method and system for implementing store buffer allocation

System and method for avoiding deadlocks when performing storage updates in a multi-processor environment

Systems and methods for processing buffer data retirement conditions

Systems and methods for processing buffer data retirement conditions