Ronald E. Freking

Bandwidth limiting on generated PCIe packets from debug source

Bandwidth limiting on generated PCIE packets from debug source

Versatile lane configuration using a PCIe PIe-8 interface

Using a PCI standard hot plug controller to modify the hierarchy of a distributed switch

Versatile lane configuration using a PCIe PIE-8 interface

External settings that reconfigure the error handling behavior of a distributed PCIe switch

External settings that reconfigure the error handling behavior of a distributed PCIe switch

Using a PCI standard hot plug controller to modify the hierarchy of a distributed switch

Transmitting retry request associated with non-posted command via response credit channel

Moving ownership of a device between compute elements

Managing memory refreshes

DYNAMICALLY SCALABLE QUEUES FOR PERFORMANCE DRIVEN PCI EXPRESS MEMORY TRAFFIC

Techniques for Handling Commands in an Ordered Command Stream

Method for Creating Data Transfer Packets With Embedded Management Information

STRUCTURE FOR DYNAMICALLY SCALABLE QUEUES FOR PERFORMANCE DRIVEN PCI EXPRESS MEMORY TRAFFIC

Dynamically scalable queues for performance driven PCI express memory traffic

Method and Apparatus for Enabling Virtual Channels Within A Peripheral Component Interconnect (PCI) Express Bus

System and method of implementing multiple internal virtual channels based on a single external virtual channel