Austin, Texas
United States
36
2019-08-15
The entities that hold a legal rights for patent applications filed by inventor Abernathy Christopher M.:
Christopher M. Abernathy from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Thread transition management
#2 | 2019-08-15Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file
#3 | 2018-12-06Thread transition management
#4 | 2017-10-19Thread transition management
#5 | 2016-06-02Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers
#6 | 2014-09-11Thread transition management
#7 | 2014-05-01EFFICIENT USAGE OF A REGISTER FILE MAPPER MAPPING STRUCTURE
#8 | 2014-05-01Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file
#9 | 2014-05-01Efficient usage of a multi-level register file utilizing a register file bypass
#10 | 2014-01-16Active power dissipation detection based on erroneus clock gating equations
#11 | 2013-12-26Instruction tracking system for processors
#12 | 2012-08-23Thread transition management
#13 | 2012-08-09Multi-level register file supporting multiple threads
#14 | 2012-03-22Multi-level register file supporting multiple threads
#15 | 2011-12-08Instruction tracking system for processors
#16 | 2011-11-17Register file supporting transactional processing
#17 | 2010-09-30Issuing instructions in-order in an out-of-order processor using false dependencies
#18 | 2010-09-30Tracking deallocated load instructions using a dependence matrix
#19 | 2010-03-25Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system
#20 | 2010-03-04System and method for double-issue instructions using a dependency matrix
#21 | 2010-03-04System and method for double-issue instructions using a dependency matrix and a side issue queue
#22 | 2009-11-26Method to reduce power consumption of a register file with multi SMT support
#23 | 2009-04-30System and Method for Issuing Load-Dependent Instructions from an Issue Queue in a Processing Unit
#24 | 2009-02-12Handling data cache misses out-of-order for asynchronous pipelines
#25 | 2009-01-01Issue unit for placing a processor into a gradual slow mode of operation
#26 | 2009-01-01Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition
#27 | 2008-10-02Using a Register File as Either a Rename Buffer or an Architected Register File
#28 | 2008-08-14Method and system for restoring register mapper states for an out-of-order microprocessor
#29 | 2008-05-29METHOD AND SYSTEM FOR ON-DEMAND SCRATCH REGISTER RENAMING
#30 | 2008-01-17System and Method for Streaming High Frequency Trace Data Off-Chip
#31 | 2008-01-17Selectively engaging optional data reduction mechanisms for capturing trace data
#32 | 2007-10-18Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
#33 | 2007-10-18Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
#34 | 2007-10-04Method and system for on-demand scratch register renaming
#35 | 2007-08-02Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines
#36 | 2007-04-19Method for dynamically choosing between varying processor error resolutions
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