Boise, Idaho
United States
25
2025-10-30
The entities that hold a legal rights for patent applications filed by inventor Marquart Todd A.:
Todd A. Marquart from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SECTION YIELDING IN STACKED MEMORY ARCHITECTURES
#2 | 2024-12-05PARITY DATA IN DYNAMIC RANDOM ACCESS MEMORY (DRAM)
#3 | 2023-06-15Parity data in dynamic random access memory (DRAM)
#4 | 2023-02-09Partitioned memory having error detection capability
#5 | 2023-01-19Memory sub-system event log management
#6 | 2022-11-03Separate partition for buffer and snapshot memory
#7 | 2022-09-15Partitions within snapshot memory for buffer and snapshot memory
#8 | 2022-07-07Read voltage calibration for copyback operation
#9 | 2022-06-23Threshold voltage distribution adjustment for buffer
#10 | 2022-06-23Parity data in dynamic random access memory (DRAM)
#11 | 2022-06-16Trims corresponding to program/erase cycles
#12 | 2022-03-03Read voltage calibration for copyback operation
#13 | 2022-03-03Separate trims for buffer and snapshot
#14 | 2022-03-03Memory sub-system event log management
#15 | 2022-03-03Data management during a copyback operation
#16 | 2022-02-24TRIM DETERMINATION BASED ON POWER AVAILABILITY
#17 | 2022-02-17Threshold voltage based on program/erase cycles
#18 | 2022-02-17Threshold voltage distribution adjustment for buffer
#19 | 2022-02-17Partitioned memory having error detection capability
#20 | 2022-02-17Partitions within snapshot memory for buffer and snapshot memory
#21 | 2022-02-17Separate partition for buffer and snapshot memory
#22 | 2022-02-17Trims corresponding to logical unit quantity
#23 | 2019-11-21Adaptive scan frequency for detecting errors in a memory system
#24 | 2013-12-26WEAR LEVELING MEMORY USING ERROR RATE
#25 | 2013-04-04Lifetime markers for memory devices
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