H. Montgomery MANNING

Memory Circuitry And Method Used In Forming Memory Circuitry

METHODS FOR FORMING COMPOSITE ARMOR PLATES USING ORDERED NANOTUBE FABRICS

PROTECTIVE ARMOR USING ORDERED NANOTUBE FABRICS

Nonvolatile nanotube switches with reduced switching voltages and currents

Ordered Nanotube Fabrics

Nonvolatile nanotube switches and systems using same

Microfluidic control surfaces using ordered nanotube fabrics

Methods for arranging nanoscopic elements within networks, fabrics and films

Methods for forming nanotube fabric layers with increased density

Non-volatile composite nanoscopic fabric NAND memory arrays and methods of making same

Cross point arrays of 1-R nonvolatile resistive change memory cells using continuous nanotube fabrics

Methods for passivating a carbonic nanolayer

METHOD AND APPARATUS FOR FABRICATING A MEMORY DEVICE WITH A DIELECTRIC ETCH STOP LAYER

Methods for passivating a carbonic nanolayer

Carbon based nonvolatile cross point memory incorporating carbon based diode select devices and MOSFET select devices for memory and logic applications

Methods for passivating a carbonic nanolayer

Reverse construction integrated circuit

Processes and apparatus having a semiconductor fin

Semiconductor constructions containing tubular capacitor storage nodes, and retaining structures along portions of the tubular capacitor storage nodes

Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects

Methods for adjusting the conductivity range of a nanotube fabric layer

Contact formation

Methods for arranging nanoscopic elements within networks, fabrics, and films

Efficient pitch multiplication process

DRAM layout with vertical FETs and method of formation

Methods for arranging nanotube elements within nanotube fabrics and films

Methods of forming integrated circuit devices

Methods for passivating a carbonic nanolayer

Compact electrical switching devices with nanotube elements, and methods of making same

Processes and apparatus having a semiconductor fin

Two-terminal nanotube devices including a nanotube bridge and methods of making same

Semiconductor constructions

Reverse construction memory cell

Memory cell, pair of memory cells, and memory array

Semiconductor fuse arrangements

Methods of forming a plurality of capacitors

Contact formation

Efficient pitch multiplication process

NRAM arrays with nanotube blocks, nanotube traces, and nanotube planes and methods of making same

Methods of forming integrated circuit devices

Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same

Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same

Contact formation

Processes and apparatus having a semiconductor fin

Efficient pitch multiplication process

Memory device with non-orthogonal word and bit lines

Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon

Methods of forming semiconductor constructions

Contact formation

Array of capacitors with electrically insulative rings

Methods of forming a plurality of capacitors

Method for forming memory cell and device

Immersion photolithography scanner

Methods of forming a plurality of capacitors

Methods of forming pluralities of capacitors

Semiconductor constructions containing tubular capacitor storage nodes, and retaining structures along portions of the tubular capacitor storage nodes

Semiconductor constructions, and methods of forming capacitor devices

Methods of forming pluralities of capacitors

Reverse construction memory cell

Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects

Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects

Method and apparatus for fabricating a memory device with a dielectric etch stop layer

Method and apparatus for fabricating a memory device with a dielectric etch stop layer

Methods of forming pluralities of capacitors

Methods of forming a plurality of capacitors

Method and apparatus for fabricating a memory device with a dielectric etch stop layer

Methods of forming vertical transistor structures

Methods of forming vertical transistor structures

Methods of forming field effect transistors

Methods of forming capacitors

Memory cell, device, and system

Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects

Methods of forming a plurality of capacitors

Methods of forming gatelines and transistor devices

Semiconductor constructions

Methods of forming plurality of capacitor devices

Methods of forming a plurality of capacitor devices

Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects

Methods of forming a plurality of capacitors

Methods of forming vertical transistor structures

Methods of forming gatelines and transistor devices

Semiconductor constructions

Stepped gate configuration for non-volatile memory

Stepped gate configuration for non-volatile memory

Stepped gate configuration for non-volatile memory

Stepped gate configuration for non-volatile memory

Methods of forming field effect transistors

Arrangements of fuse-type constructions

Gated field effect devices

Methods of forming semiconductor structures and capacitor devices

Methods of forming semiconductor fuse arrangements

Methods of forming trench isolation regions with nitride liner

Methods of forming trench isolation regions

Methods of forming a gated device

Method of fabricating integrated circuitry

Semiconductor constructions

Gated field effect device comprising gate dielectric having different K regions

Method and apparatus for fabricating a memory device with a dielectric etch stop layer

Methods of forming trench isolation regions

Semiconductor devices, capacitor antifuses, dynamic random access memories, and cell plate bias connection methods