Plano, Texas
United States
58
2022-06-16
The entities that hold a legal rights for patent applications filed by inventor Chatterjee Amitava:
Amitava Chatterjee from Plano, US has applied for patents for these inventions. The list has both pending applications and granted patents:
ESD protection circuit with isolated SCR for negative voltage operation
#2 | 2018-12-06ESD protection circuit with isolated SCR for negative voltage operation
#3 | 2018-12-06ESD protection circuit with isolated SCR for negative voltage operation
#4 | 2017-11-30I-shaped gate electrode for improved sub-threshold MOSFET performance
#5 | 2016-12-22High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit
#6 | 2016-11-03Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
#7 | 2016-03-17Drain extended CMOS with counter-doped drain extension
#8 | 2016-03-17Deep collector vertical bipolar transistor with enhanced gain
#9 | 2016-02-04Low cost demos transistor with improved CHC immunity
#10 | 2015-12-31I-shaped gate electrode for improved sub-threshold MOSFET performance
#11 | 2015-10-15ESD protection circuit with isolated SCR for negative voltage operation
#12 | 2015-09-03Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
#13 | 2015-09-03Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
#14 | 2015-07-02Low cost demos transistor with improved CHC immunity
#15 | 2015-07-02Deep collector vertical bipolar transistor with enhanced gain
#16 | 2014-10-02Analog floating-gate capacitor with improved data retention in a silicided integrated circuit
#17 | 2014-09-11Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
#18 | 2014-08-14Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells
#19 | 2014-07-03High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit
#20 | 2014-07-03DEMOS formed with a through gate implant
#21 | 2014-05-08ESD protection circuit with isolated SCR for negative voltage operation
#22 | 2014-04-17I-SHAPED GATE ELECTRODE FOR IMPROVED SUB-THRESHOLD MOSFET PERFORMANCE
#23 | 2014-03-13Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells
#24 | 2014-03-06Drain extended CMOS with counter-doped drain extension
#25 | 2014-02-13MOS transistors having reduced leakage well-substrate junctions
#26 | 2014-01-23Pocket counterdoping for gate-edge diode leakage reduction
#27 | 2014-01-02Analog floating-gate capacitor with improved data retention in a silicided integrated circuit
#28 | 2012-11-01SRAM cell parameter optimization
#29 | 2012-05-10Drain extended CMOS with counter-doped drain extension
#30 | 2010-10-28Method for measuring interface traps in thin gate oxide MOSFETS
#31 | 2010-07-01Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom
#32 | 2010-07-01Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom
#33 | 2009-10-15Application of different isolation schemes for logic and embedded memory
#34 | 2009-05-28Semiconductor interconnect
#35 | 2008-07-03Sidewall spacer pullback scheme
#36 | 2008-04-24Method for measuring interface traps in thin gate oxide MOSFETs
#37 | 2008-01-03Application of different isolation schemes for logic and embedded memory
#38 | 2007-12-13Method of manufacturing gate sidewalls that avoids recessing
#39 | 2007-12-13Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs
#40 | 2006-10-12Isolation region formation that controllably induces stress in active regions
#41 | 2006-09-14Method for manufacturing a semiconductor device using a sidewall spacer etchback
#42 | 2006-08-24Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
#43 | 2006-04-20Application of different isolation schemes for logic and embedded memory
#44 | 2006-02-09Lateral bipolar junction transistor in CMOS flow
#45 | 2006-02-02Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI)
#46 | 2006-02-02Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)
#47 | 2006-02-02Shallow trench isolation method
#48 | 2006-02-02Method for manufacturing improved sidewall structures for use in semiconductor devices
#49 | 2006-01-26Silicide method for CMOS integrated circuits
#50 | 2006-01-17Forming lateral bipolar junction transistor in CMOS flow
#51 | 2005-12-29Multi-layer reducible sidewall process
#52 | 2005-07-07Design method and system for optimum performance in integrated circuits that use power management
#53 | 2005-07-07Application of different isolation schemes for logic and embedded memory
#54 | 2005-06-09Modeling process for integrated circuit film resistors
#55 | 2005-04-28Application of different isolation schemes for logic and embedded memory
#56 | 2005-03-29Asymmetrical devices for short gate length performance with disposable sidewall
#57 | 2005-03-22Compensated-well electrostatic discharge protection devices
#58 | 2005-02-22Vertical bipolar transistor formed using CMOS processes
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