Tainan
Taiwan
46
2024-11-14
The entities that hold a legal rights for patent applications filed by inventor Liu Po-Wei:
Po-Wei Liu from Tainan, TW has applied for patents for these inventions. The list has both pending applications and granted patents:
FIELD EFFECT TRANSISTOR WITH TOP-PROTECTED GATE ELECTRODE AND METHODS FOR FORMING THE SAME
#2 | 2024-09-05ONON sidewall structure for memory device and method for making the same
#3 | 2024-03-21SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHOD THEREOF
#4 | 2024-03-14BCD DEVICE LAYOUT AREA DEFINED BY A DEEP TRENCH ISOLATION STRUCTURE AND METHODS FOR FORMING THE SAME
#5 | 2023-11-09Strap-cell architecture for embedded memory
#6 | 2023-10-19ONON sidewall structure for memory device and method for making the same
#7 | 2023-09-14Device-region layout for embedded flash
#8 | 2023-04-13Strap-cell architecture for embedded memory
#9 | 2023-01-19Semiconductor structure
#10 | 2022-12-01Deep trench isolation structure and method of making the same
#11 | 2022-11-03Selective polysilicon growth for deep trench polysilicon isolation structure
#12 | 2022-11-03BCD device layout area defined by a deep trench isolation structure and methods for forming the same
#13 | 2022-02-10Device-region layout for embedded flash
#14 | 2021-12-23Control gate strap layout to improve a word line etch process window
#15 | 2021-09-09Semiconductor device and manufacturing method thereof
#16 | 2021-07-29Deep trench isolation structure and method of making the same
#17 | 2021-07-22Semiconductor device and manufacturing method thereof
#18 | 2021-07-01Semiconductor structure and method for forming the same
#19 | 2021-06-17Strap-cell architecture for embedded memory
#20 | 2021-04-29Selective polysilicon growth for deep trench polysilicon isolation structure
#21 | 2021-03-11Device-region layout for embedded flash
#22 | 2020-07-09Method to reduce kink effect in semiconductor devices
#23 | 2020-06-18Non-volatile memory semiconductor device with electrostatic discharge protection, planarization layers, and manufacturing method thereof
#24 | 2020-05-21Semiconductor device and manufacturing method thereof
#25 | 2020-04-02Strap-cell architecture for embedded memory
#26 | 2020-04-02Device-region layout for embedded flash
#27 | 2020-03-26Control gate strap layout to improve a word line etch process window
#28 | 2019-11-21Method to reduce kink effect in semiconductor devices
#29 | 2019-07-25Semiconductor device and manufacturing method thereof
#30 | 2019-05-23Semiconductor device and manufacturing method thereof
#31 | 2019-02-28Semiconductor structure for memory device and method for forming the same
#32 | 2018-11-01Semiconductor device and manufacturing method thereof
#33 | 2018-07-12Semiconductor device and manufacturing method thereof
#34 | 2018-05-31Non-volatile memory semiconductor device and manufacturing method thereof
#35 | 2018-03-01Semiconductor memory device and manufacturing method thereof
#36 | 2018-02-01Semiconductor device and method for manufacturing the same
#37 | 2018-01-18Semiconductor device and manufacturing method thereof
#38 | 2017-08-08Semiconductor structure and fabricating method thereof
#39 | 2016-08-04Logic compatible flash memory cells
#40 | 2016-02-04High endurance non-volatile memory cell
#41 | 2016-01-14Method to improve memory cell erasure
#42 | 2015-07-30Method of forming a logic compatible flash memory
#43 | 2015-01-22Architecture to improve cell size for compact array of split gate flash cell with buried common source structure
#44 | 2014-09-18Architecture to improve cell size for compact array of split gate flash cell
#45 | 2014-06-05Methods and apparatus for non-volatile memory cells with increased programming efficiency
#46 | 2012-11-29Fin-like field effect transistor (FinFET) non-volatile random access memory (NVRAM) device with bottom erase gate
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