Sergey Shumarayev

Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits

Adaptive equalization methods and apparatus for programmable logic devices

Voltage-controlled oscillator methods and apparatus

Method and apparatus for standby voltage offset cancellation

Heterogeneous transceiver architecture for wide range programmability of programmable logic devices

Digital adaptation circuitry and methods for programmable logic devices

Clock signal circuitry for multi-channel data signaling

Adaptive equalization methods and apparatus for programmable logic devices

Voltage-controlled oscillator methods and apparatus

Systems and methods for simulating link performance

Dynamically-adjustable differential output drivers

Heterogeneous transceiver architecture for wide range programmability of programmable logic devices

Interconnection and input/output resources for programmable logic integrated circuit devices

Signal adjustment receiver circuitry

SIGNAL ADJUSTMENT RECEIVER CIRCUITRY

Flexible signal detect for programmable logic device serial interface

Signal amplitude detection circuitry without pattern dependencies for high-speed serial links

Adaptive equalization methods and apparatus

Comparator offset cancellation assisted by PLD resources

Wide range and dynamically reconfigurable clock data recovery architecture

Techniques for dynamically adjusting the frequency range of phase-locked loops

Adaptive equalization methods and apparatus

Variable-bandwidth loop filter methods and apparatus

Wide operating-frequency range voltage controlled oscillators

Integration of high-speed serial interface circuitry into programmable logic device architectures

Systems and methods for mitigating phase jitter in a periodic signal

Dynamically-adjustable differential output drivers

Dynamic bias circuit

Phase lock loop and method for operating the same

Interconnection and input/output resources for programmable logic integrated circuit devices

Digital adaptation circuitry and methods for programmable logic devices

Economical, scalable transceiver jitter test

Heterogeneous transceiver architecture for wide range programmability of programmable logic devices

Integrated circuit serializers with two-phase global master clocks

Adjustable differential input and output drivers

Signal adjustment receiver circuitry

Signal adjustment receiver circuitry

Interconnection resources for programmable logic integrated circuit devices

Programmable digital equalization control circuitry and methods

Dynamically adjustable termination impedance control techniques

Interconnection and input/output resources for programmable logic integrated circuit devices

Circuitry and methods for programmably adjusting the duty cycles of serial data signals

Programmable receiver equalization circuitry and methods

Clock data recovery circuitry and phase locked loop circuitry with dynamically adjustable bandwidths

Programmable slew rate control for differential output

Programmable termination with DC voltage level control

Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices

APPARATUS AND METHODS FOR ADJUSTING PERFORMANCE CHARACTERISTICS OF CIRCUITRY IN PROGRAMMABLE LOGIC DEVICES

Dynamically adjustable signal detector

Interconnection and input/output resources for programmable logic integrated circuit devices

Programmable termination with DC voltage level control

Dynamically adjustable signal detector

Adjustable differential input and output drivers

Interconnection resources for programmable logic integrated circuit devices

Dynamically-adjustable differential output drivers

Interconnection resources for programmable logic integrated circuit devices

Interconnection and input/output resources for programmable logic integrated circuit devices

Dynamically adjustable termination impedance control techniques

Adjustable differential input and output drivers