Ossining, New York
United States
25
2021-04-01
The entities that hold a legal rights for patent applications filed by inventor May Cathy:
Cathy May from Ossining, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Translation load instruction with access protection
#2 | 2020-06-25Interruptible translation entry invalidation in a multithreaded data processing system
#3 | 2019-01-31Hardware based isolation for secure execution of virtual machines
#4 | 2018-12-27Efficient enforcement of barriers with respect to memory move sequences
#5 | 2018-02-22Memory move instruction sequence including a stream of copy-type and paste-type instructions
#6 | 2018-02-22Efficient enforcement of barriers with respect to memory move sequences
#7 | 2014-04-24Conditional transaction abort and precise abort handling
#8 | 2014-03-20Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories
#9 | 2014-03-13Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories
#10 | 2014-03-13Determining failure context in hardware transactional memories
#11 | 2014-03-13Apparatus for determining failure context in hardware transactional memories
#12 | 2014-02-13Interaction of transactional storage accesses with other atomic semantics
#13 | 2014-02-13Transaction check instruction for memory transactions
#14 | 2014-02-13Transaction check instruction for memory transactions
#15 | 2014-02-06Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accesses
#16 | 2014-02-06Rewind only transactions in a data processing system supporting transactional storage accesses
#17 | 2014-01-09Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses
#18 | 2014-01-09ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES
#19 | 2012-09-27Transactional memory preemption mechanism
#20 | 2012-07-19Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition
#21 | 2012-04-05Transactional memory preemption mechanism
#22 | 2011-12-01Transactional memory system supporting unbroken suspended execution
#23 | 2011-08-25Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition
#24 | 2010-10-21Specifying an access hint for prefetching partial cache block data in a cache hierarchy
#25 | 2010-10-21Specifying an access hint for prefetching limited use data in a cache hierarchy
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