Colin Eddy

L1D to L2 eviction

Tablewalk takeover

Cache memory budgeted by ways based on memory access type

System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructions

System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction

System and method of determining memory ownership on cache line basis for detecting self-modifying code

System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundaries

Prefetching with level of aggressiveness based on effectiveness by memory access type

Set associative cache memory with heterogeneous replacement policy

Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type

Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor

Cache replacement policy that considers memory access type

Cache memory budgeted by chunks based on memory access type

Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor

Mechanism to preclude load replays dependent on page walks in an out-of-order processor

Apparatus and method for programmable load replay preclusion

Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor

Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor

Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor

Load replay precluding mechanism

Mechanism to preclude uncacheable-dependent load replays in out-of-order processor

Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor

Processor including single invalidate page instruction

Mechanism to preclude shared RAM-dependent load replays in an out-of-order processor

Mechanism to preclude I/O-dependent load replays in an out-of-order processor

Processor including load EPT instruction

CACHE SYSTEM WITH A PRIMARY CACHE AND AN OVERFLOW FIFO CACHE

Power saving mechanism to reduce load replays in out-of-order processor

Fully associative cache memory budgeted by memory access type

Address translation cache that supports simultaneous invalidation of common context entries

Simultaneous invalidation of all address translation cache entries associated with an X86 process context identifier

Cache system with a primary cache and an overflow cache that use different indexing schemes

Programmable load replay precluding mechanism

Apparatus and method for programmable load replay preclusion

Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor

Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor

Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor

Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor

Mechanism to preclude shared ram-dependent load replays in an out-of-order processor

Power saving mechanism to reduce load replays in out-of-order processor

Programmable load replay precluding mechanism

Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor

Mechanism to preclude load replays dependent on page walks in an out-of-order processor

Load replay precluding mechanism

Mechanism to preclude uncacheable-dependent load replays in out-of-order processor

Mechanism to preclude I/O-dependent load replays in an out-of-order processor

Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor

System and method for performing hardware prefetch tablewalks having lowest tablewalk priority

Efficient address translation caching in a processor that supports a large number of different address spaces

Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry

Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match

Microprocessor that translates conditional load/store instructions into variable number of microinstructions

Conditional store instructions in an out-of-order execution microprocessor

Conditional load instructions in an out-of-order execution microprocessor

PREFETCHING OF NEXT PHYSICALLY SEQUENTIAL CACHE LINE AFTER CACHE LINE THAT INCLUDES LOADED PAGE TABLE ENTRY

Efficient data prefetching in the presence of load hits

Efficient data prefetching in the presence of load hits

Prefetching of next physically sequential cache line after cache line that includes loaded page table entry

Multi-modal data prefetcher

Avoiding memory access latency by returning hit-modified when holding non-modified data

Fast REP STOS using grabline operations

Efficient pseudo-LRU for colliding accesses

Microprocessor that performs a two-pass breakpoint check for a cache line-crossing load/store operation

Store-to-load forwarding based on load/store address computation source information comparisons

Microprocessor with ALU integrated into store unit

Microprocessor with ALU integrated into load unit

Efficient data prefetching in the presence of load hits

Guaranteed prefetch instruction

Data cache with modified bit array

Data cache with modified bit array

Low power high speed load-store collision detector

Prefetching of next physically sequential cache line after cache line that includes loaded page table entry