Krishna R. Tunga

Mitigating cooldown peeling stress during chip package assembly

#2 | 2022-03-24

US20220093556A1

Asymmetric die bonding

#3 | 2022-02-03

US20220032000A1

Internet of things (IoT) real-time response to defined symptoms

#4 | 2021-10-14

US20210320056A1

Enlarged conductive pad structures for enhanced chip bond assembly yield

#5 | 2021-08-05

US20210242139A1

Mitigating thermal-mechanical strain and warpage of an organic laminate substrate

#6 | 2021-04-15

US20210110727A1

Language learning and speech enhancement through natural language processing

#7 | 2020-10-15

US20200328177A1

Mitigating cracking within integrated circuit (IC) device carrier

#8 | 2020-09-24

US20200303339A1

Lead-free column interconnect

#9 | 2020-08-25

US16409321

Decoupling capacitor stiffener

#10 | 2020-05-21

US20200160228A1

COGNITIVE COMPUTING DEVICE FOR PREDICTING AN OPTIMAL STRATEGY IN COMPETITIVE CIRCUMSTANCES

#11 | 2020-03-19

US20200090542A1

Behavior-based interactive educational sessions

#12 | 2020-02-27

US20200066127A1

Internet of things (IOT) real-time response to defined symptoms

#13 | 2020-02-13

US20200051447A1

COGNITIVE TOOL FOR TEACHING GENERLIZATION OF OBJECTS TO A PERSON

#14 | 2020-01-30

US20200035593A1

Connected plane stiffener within integrated circuit chip carrier

#15 | 2020-01-09

US20200013732A1

Laminated stiffener to control the warpage of electronic chip carriers

#16 | 2019-11-28

US20190357843A1

OPTIMIZED INDIVIDUAL SLEEP PATTERNS

#17 | 2019-09-26

US20190295921A1

Managing thermal warpage of a laminate

#18 | 2019-08-29

US20190267332A1

Method of forming an electronic package

#19 | 2019-08-22

US20190259683A1

Multipart lid for a semiconductor package with multiple components

#20 | 2019-05-30

US20190164864A1

Multipart lid for a semiconductor package with multiple components

#21 | 2019-05-16

US20190148260A1

Electronic package with tapered pedestal

#22 | 2019-04-25

US20190122574A1

Language learning and speech enhancement through natural language processing

#23 | 2018-12-27

US20180368757A1

Optimized individual sleep patterns

#24 | 2018-12-27

US20180368756A1

Optimized individual sleep patterns

#25 | 2018-10-18

US20180301355A1

Control warpage in a semiconductor chip package

#26 | 2018-04-19

US20180108626A1

Final passivation for wafer level warpage and ULK stress reduction

#27 | 2018-04-17

US15634237

Determining crackstop strength of integrated circuit assembly at the wafer level

#28 | 2018-03-22

US20180082922A1

Electronic package cover having underside rib

#29 | 2018-03-22

US20180082919A1

Electronic package cover having underside rib

#30 | 2018-03-15

US20180076101A1

Test cell for laminate and method

#31 | 2018-03-01

US20180061800A1

Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress

#32 | 2018-03-01

US20180061799A1

Reduction of solder interconnect stress

#33 | 2018-01-09

US15251325

Reduction of solder interconnect stress

#34 | 2017-12-05

US15271980

Electronic package cover having underside rib

#35 | 2017-09-05

US15292433

Final passivation for wafer level warpage and ULK stress reduction

#36 | 2017-06-22

US20170178982A1

Test cell for laminate and method

#37 | 2017-02-07

US15006567

In-plane copper imbalance for warpage prediction

#38 | 2014-01-30

US20140027898A1

Multichip electronic packages and methods of manufacture

#39 | 2014-01-16

US20140015387A1

Non-hermetic sealed multi-chip module package

#40 | 2012-12-27

US20120326294A1