Dublin, California
United States
72
2025-11-20
The entities that hold a legal rights for patent applications filed by inventor GOEL Sandeep Kumar:
Sandeep Kumar GOEL from Dublin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
#2 | 2024-11-28FUNCTION SAFETY AND FAULT MANAGEMENT MODELING AT ELECTRICAL SYSTEM LEVEL (ESL)
#3 | 2024-10-31Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis
#4 | 2024-06-20NETWORK-ON-CHIP SYSTEM AND A METHOD OF GENERATING THE SAME
#5 | 2024-04-25SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
#6 | 2024-03-14SYSTEMS AND METHODS TO DETECT CELL-INTERNAL DEFECTS
#7 | 2024-01-18DEVICE WITH SELF-AUTHENTICATION
#8 | 2023-11-30FAULT DIAGNOSTICS
#9 | 2023-11-16Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis
#10 | 2023-04-13Scan architecture for interconnect testing in 3D integrated circuits
#11 | 2023-02-23Network-on-chip system and a method of generating the same
#12 | 2023-01-19SYSTEMS AND METHODS FOR MODELING VIA DEFECT
#13 | 2022-09-15Function safety and fault management modeling at electrical system level (ESL)
#14 | 2022-07-28FAULT DETECTION OF CIRCUIT BASED ON VIRTUAL DEFECTS
#15 | 2022-07-21Systems and methods to detect cell-internal defects
#16 | 2021-12-30Systems and methods to detect cell-internal defects
#17 | 2021-11-11Fault diagnostics
#18 | 2021-09-09Phase-locked loop monitor circuit
#19 | 2021-07-15Device with self-authentication
#20 | 2021-06-24Method and system for reducing migration errors
#21 | 2020-12-31Function safety and fault management modeling at electrical system level (ESL)
#22 | 2020-12-03Test probing structure
#23 | 2020-11-26System and method for ESL modeling of machine learning
#24 | 2020-09-24Phase-locked loop monitor circuit
#25 | 2020-09-03Network-on-chip system and a method of generating the same
#26 | 2020-04-23Scan architecture for interconnect testing in 3D integrated circuits
#27 | 2020-01-30Image processing apparatus having overlapping sub-regions
#28 | 2020-01-02Machine-learning based scan design enablement platform
#29 | 2019-10-31Power estimation
#30 | 2019-07-25Phase-locked loop monitor circuit
#31 | 2019-04-04Device with self-authentication
#32 | 2019-01-31Function safety and fault management modeling at electrical system level (ESL)
#33 | 2018-12-20Dynamic frequency scaling
#34 | 2018-11-01Electrical system level (ESL) battery discharge simulation
#35 | 2018-06-14Device and method for robustness verification
#36 | 2018-05-31Phase-locked loop monitor circuit
#37 | 2018-05-31Method and system for functional safety verification
#38 | 2018-03-08Network-on-chip system and a method of generating the same
#39 | 2018-02-08Test probing structure
#40 | 2018-02-01Circuit and method for diagnosing scan chain failures
#41 | 2017-12-07Scan architecture for interconnect testing in 3D integrated circuits
#42 | 2017-11-30Power estimation
#43 | 2017-11-30Processor power estimation
#44 | 2017-10-26Bidirectional scan chain structure and method
#45 | 2017-10-19Power consumption estimation method for system on chip (SOC), system for implementing the method
#46 | 2017-06-08Method of component partitions on system on chip and device thereof
#47 | 2017-04-06Power state coverage metric and method for estimating the same
#48 | 2017-03-16System and method for system-level parameter estimation
#49 | 2017-03-16System and method for estimating performance, power, area and cost (PPAC)
#50 | 2016-10-20Wafer on wafer stack method of forming and method of using the same
#51 | 2016-09-22Method, device and computer program product for circuit testing
#52 | 2016-09-15Methods and systems for circuit fault diagnosis
#53 | 2016-09-08Method and apparatus for interconnect test
#54 | 2016-05-12Circuit and method for monolithic stacked integrated circuit testing
#55 | 2016-02-18Image processing apparatus on integrated circuit and method thereof
#56 | 2016-02-18Wafer on wafer stack method of forming and method of using the same
#57 | 2016-02-11Circuit and method for diagnosing scan chain failures
#58 | 2016-01-21Interposer defect coverage metric and method to maximize the same
#59 | 2016-01-14System for and method of semiconductor fault detection
#60 | 2015-12-10Circuit and method for monolithic stacked integrated circuit testing
#61 | 2015-12-03System for and method of semiconductor fault detection
#62 | 2015-07-16System and method of adaptive voltage frequency scaling
#63 | 2015-04-02Circuit and method for monolithic stacked integrated circuit testing
#64 | 2015-03-19Circuit and method for monolithic stacked integrated circuit testing
#65 | 2015-03-19Circuit and method for monolithic stacked integrated circuit testing
#66 | 2015-02-26Interposer defect coverage metric and method to maximize the same
#67 | 2014-09-18Method and apparatus for interconnect test
#68 | 2014-09-02Reducing design verification time while maximizing system functional coverage
#69 | 2014-03-06Circuit and method for diagnosing scan chain failures
#70 | 2014-01-16System and method for testing stacked dies
#71 | 2014-01-16System and method for testing stacked dies
#72 | 2013-10-15System and method for testing stacked dies
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