Andrew E. Horch

One-time programmable bitcell with diode under anti-fuse

One-time programmable bitcell with partially native select device

One-time programmable bitcell with native anti-fuse

One-time programmable memory using rupturing of gate insulation

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

One-time programmable bitcell with native anti-fuse

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

NVM device using FN tunneling with parallel powered source and drain

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

Very dense nonvolatile memory bitcell

Fabricating a gate oxide

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

RFID tag having non-volatile memory device having floating-gate FETs with different source-gate and drain-gate border lengths

NVM bitcell with a replacement control gate and additional floating gate

Very dense NVM bitcell

METHOD FOR DEPOSITING A DIELECTRIC ONTO A FLOATING GATE FOR STRAINED SEMICONDUCTOR DEVICES

One time programmable memory test structures and methods

Non-volatile memory cell with BTBT programming

Vertical thyristor-based memory with trench isolation and method of fabrication thereof

RFID tag circuit die with shielding layer to control I/O bump flow

Non-volatile memory cell with BTBT programming

Non-volatile memory cell circuit with programming through band-to-band tunneling and impact ionization gate current

Etch before grind for semiconductor die singulation

Vertical thyristor-based memory with trench isolation and its method of fabrication

Multi-level non-volatile memory cell with high-VT enhanced BTBT device

Non-volatile memory devices having floating-gates FETs with different source-gate and drain-gate border lengths

RFID tag having non-volatile memory device having floating-gate FETs with different source-gate and drain-gate border lengths

Non-volatile memory with programming through band-to-band tunneling and impact ionization gate current

Non-volatile memory cell circuit with programming through band-to-band tunneling and impact ionization gate current

Semiconductor device incorporating thyristor-based memory and strained silicon

INTEGRATED CIRCUIT TEST RESULT COMMUNICATION

Wireless functional testing of RFID tag

On die RFID tag antenna

Semiconductor device with leakage implant and method of fabrication