Inventor profile of:

Andreas Nowatzyk

City:

San Jose, California

Country:

United States

Published Applications:

20

Last publication date:

2023-03-02

Top Assignees for applications by Andreas Nowatzyk

The entities that hold a legal rights for patent applications filed by inventor Nowatzyk Andreas:

Recent patent applications by Nowatzyk Andreas

Andreas Nowatzyk from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-03-02
US20230069152A1
Physics

Low latency host processor to coherent device interaction

#2 | 2023-01-26
US20230028825A1
Physics

Coherence-based dynamic code rewriting, tracing and code coverage

#3 | 2023-01-26
US20230023256A1
Physics

Coherence-based cache-line Copy-on-Write

#4 | 2023-01-26
US20230022096A1
Physics

Coherence-based attack detection

#5 | 2023-01-05
US20230004497A1
Physics

Smart prefetching for remote memory

#6 | 2023-01-05
US20230004496A1
Physics

Smart prefetching for remote memory

#7 | 2022-12-29
US20220414017A1
Physics

Method and system for tracking state of cache lines

#8 | 2018-12-06
US20180348821A1
Physics

Bend limit film

#9 | 2018-07-05
US20180188536A1
Physics

NEAR EYE DISPLAY MULTI-COMPONENT DIMMING SYSTEM

#10 | 2016-10-20
US20160309065A1
Electricity

LIGHT GUIDED IMAGE PLANE TILED ARRAYS WITH DENSE FIBER OPTIC BUNDLES FOR LIGHT-FIELD AND HIGH RESOLUTION IMAGE ACQUISITION

#11 | 2014-03-06
US20140063174A1
Electricity

Mobile video conferencing with digital annotation

#12 | 2013-01-03
US20130003163A1
Physics

Passive matrix quantum dot display

#13 | 2013-01-03
US20130002614A1
Physics

Electromagnetic 3D stylus

#14 | 2012-08-16
US20120206349A1
Physics

Universal stylus device

#15 | 2012-07-12
US20120179674A1
Physics

Hardware accelerated shortest path computation

#16 | 2008-06-17
US10672960
-

System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system

#17 | 2006-01-17
US10693388
-

Scalable architecture based on single-chip multiprocessing

#18 | 2005-08-02
US10698130
-

Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants

#19 | 2005-06-28
US10769824
-

Method and system for exclusive two-level caching in a chip-multiprocessor

#20 | 2005-02-03
US20050024320A1
Physics

Surround-vision display system

InventorID:

6197 ⎘