Austin, Texas
United States
45
2017-07-27
The entities that hold a legal rights for patent applications filed by inventor Choy Jon S.:
Jon S. Choy from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Sense amplifier
#2 | 2017-06-15Charge pump circuit for providing multiplied voltage
#3 | 2017-05-23Sense amplifier
#4 | 2017-05-02Nonvolatile static random access memory (NVSRAM) system having a static random access memory (SRAM) array and a resistive memory array
#5 | 2017-03-09Charge pump circuit for providing multiplied voltage
#6 | 2017-01-26Simulation of hierarchical circuit element arrays
#7 | 2016-11-01Voltage sampling switch and method therefor
#8 | 2016-09-20Systems and methods for driving a control gate with a select gate signal in a split-gate nonvolatile memory cell
#9 | 2016-03-03Flash memory with improved read performance
#10 | 2015-12-24Control gate driver for use with split gate memory cells
#11 | 2015-11-17Latching level shifter and method of operation
#12 | 2014-09-18Negative charge pump regulation
#13 | 2014-09-11Temperature-based adaptive erase or program parallelism
#14 | 2014-08-28Sense amplifier voltage regulator
#15 | 2014-07-24Systems and methods for adaptive soft programming for non-volatile memory using temperature sensor
#16 | 2014-05-29Voltage ramp-up protection
#17 | 2014-05-29Systems and methods for controlling power in semiconductor circuits
#18 | 2014-05-27Flash memory with bias voltage for word line/row driver
#19 | 2014-05-22Non-volatile memory robust start-up using analog-to-digital converter
#20 | 2014-01-23Error detection at an oscillator
#21 | 2012-08-09Erase ramp pulse width control for non-volatile memory
#22 | 2012-05-10Non-volatile memory (NVM) erase operation with brownout recovery technique
#23 | 2012-05-10Method for programming a multi-state non-volatile memory (NVM)
#24 | 2012-01-19Soft program of a non-volatile memory block
#25 | 2011-09-15Current injector circuit for supplying a load transient in an integrated circuit
#26 | 2011-03-10Regulator having interleaved latches
#27 | 2011-02-03Latched comparator and methods therefor
#28 | 2009-06-04High-dynamic range low ripple voltage multiplier
#29 | 2009-03-05Voltage regulator for integrated circuits
#30 | 2009-02-05Method and circuit for preventing high voltage memory disturb
#31 | 2009-02-05Non-volatile memory having a dynamically adjustable soft program verify voltage level and method therefor
#32 | 2008-12-04Integrated circuit featuring a non-volatile memory with charge/discharge ramp rate control and method therefor
#33 | 2008-01-31Memory circuit using a reference for sensing
#34 | 2008-01-31Current comparison based voltage bias generator for electronic data storage devices
#35 | 2008-01-17Concurrent programming and program verification of floating gate transistor
#36 | 2007-12-06Nonvolatile memory having latching sense amplifier and method of operation
#37 | 2007-11-29Multi-level voltage adjustment
#38 | 2007-11-29FLOATING VOLTAGE SOURCE
#39 | 2007-10-09Charge pump system with reduced ripple and method therefor
#40 | 2007-09-27Slew rate control of a charge pump
#41 | 2007-08-30Non-volatile memory having a multiple block erase mode and method therefor
#42 | 2006-05-18Integrated circuit having a non-volatile memory with discharge rate control and method therefor
#43 | 2006-05-18Integrated circuit having a non-volatile memory with discharge rate control and method therefor
#44 | 2005-06-21Non-volatile memory having a bias on the source electrode for HCI programming
#45 | 2005-02-08Non-volatile memory architecture and method thereof
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