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Inventor profile of:

Vinaya Kumar Singh

City:

Noida

Country:

India

Published Applications:

7

Last publication date:

2012-01-17

Top Assignees for applications by Vinaya Kumar Singh

The entities that hold a legal rights for patent applications filed by inventor Singh Vinaya Kumar:

  • Cadence Design Systems, Inc. 7 San Jose, CA United States

Recent patent applications by Singh Vinaya Kumar

Vinaya Kumar Singh from Noida, IN has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2012-01-17
US11498472
-

Automated debugging method and system for over-constrained circuit verification environment

#2 | 2010-10-05
US11711950
-

Method and system for implementing context aware synthesis of assertions

#3 | 2010-05-04
US11712003
-

Method and system for handling assertion libraries in functional verification

#4 | 2009-06-04
US20090144683A1
Physics

Automated debugging method for over-constrained circuit verification environment

#5 | 2009-06-04
US20090144681A1
Physics

Method for providing information associated with an over-constrained event in verification of a circuit design

#6 | 2009-06-04
US20090144680A1
Physics

Method for checking a status of a signal port to identify an over-constrained event

#7 | 2008-09-23
US11281426
-

Design optimization using approximate reachability analysis

InventorID:

6225644 ⎘

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