Poughkeepsie, New York
United States
23
2021-03-11
The entities that hold a legal rights for patent applications filed by inventor CASEY Jon A.:
Jon A. CASEY from Poughkeepsie, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Polygon integrated circuit (IC) packaging
#2 | 2021-01-21Electronic device console with natural draft cooling
#3 | 2020-05-07Direct bonded heterogeneous integration packaging structures
#4 | 2019-09-26Direct bonded heterogeneous integration packaging structures
#5 | 2017-03-21Under die surface mounted electrical elements
#6 | 2016-01-21Electronic device console with natural draft cooling
#7 | 2014-01-23Electronic device console with natural draft cooling
#8 | 2012-09-13Passivation layer surface topography modifications for improved integrity in packaged assemblies
#9 | 2012-07-12Achieving mechanical and thermal stability in a multi-chip package
#10 | 2011-05-26Passivation layer surface topography modifications for improved integrity in packaged assemblies
#11 | 2010-07-22Achieving mechanical and thermal stability in a multi-chip package
#12 | 2010-02-25Enhanced thermal management for improved module reliability
#13 | 2010-02-25Tracking thermal mini-cycle stress
#14 | 2007-02-08Suspension for filling via holes in silicon and method for making the same
#15 | 2007-02-01Enhanced via structure for organic module performance
#16 | 2006-11-16Materials and method to seal vias in silicon substrates
#17 | 2005-09-15Low-K dielectric material system for IC application
#18 | 2005-08-11Electronic package repair process
#19 | 2005-07-14Method for integrating thermistor
#20 | 2005-07-12Electronic package repair process
#21 | 2005-07-07Suspension for filling via holes in silicon and method for making the same
#22 | 2005-05-19Method and apparatus for filling vias
#23 | 2005-04-12Low-k dielectric material system for IC application
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