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Inventor profile of:

Meng-Wei Chen

City:

Taichung

Country:

Taiwan

Published Applications:

Last publication date:

2021-08-26

Top Assignees for applications by Meng-Wei Chen

The entities that hold a legal rights for patent applications filed by inventor Chen Meng-Wei:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 9 Hsin-Chu, Taiwan
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 7 Hsinchu, Taiwan
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 1 Hsinchu, Taiwan
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 1 Hsin-Chu, Taiwan
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 1 , Taiwan

Recent patent applications by Chen Meng-Wei

Meng-Wei Chen from Taichung, TW has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2021-08-26

US20210263425A1

Physics

Method of fabricating reticle

#2 | 2020-11-19

US20200365520A1

Electricity

Method for forming semiconductor device structure with overlay grating

#3 | 2020-05-14

US20200150546A1

Physics

Method of fabricating reticle

#4 | 2020-02-20

US20200058595A1

Electricity

Method for forming semiconductor device structure with overlay grating

#5 | 2019-05-02

US20190131190A1

Electricity

Method for forming semiconductor device structure with overlay grating

#6 | 2019-01-03

US20190004436A1

Physics

Method of fabricating reticle

#7 | 2017-09-26

US15169565

Electricity

Material composition and process for mitigating assist feature pattern transfer

#8 | 2016-05-05

US20160124323A1

Physics

Exposure method of wafer substrate, manufacturing method of semiconductor device, and exposure tool

#9 | 2016-03-03

US20160062250A1

Physics

Lithography process and system with enhanced overlay quality

#10 | 2014-12-18

US20140367869A1

Electricity

Enhanced FinFET process overlay mark

#11 | 2014-03-06

US20140065832A1

Electricity

Enhanced FinFET process overlay mark

#12 | 2014-01-23

US20140024218A1

Electricity

Integrated circuit method with triple patterning

#13 | 2013-10-24

US20130280909A1

Electricity

Metal cut process flow

#14 | 2013-09-05

US20130230980A1

Electricity

Method of patterning a semiconductor device

#15 | 2013-04-18

US20130095662A1

Electricity

Integrated circuit method with triple patterning

#16 | 2012-06-21

US20120153441A1

Physics

Overlay mark enhancement feature

#17 | 2012-02-16

US20120038021A1

Physics

Overlay mark enhancement feature

#18 | 2011-10-06

US20110241119A1

Physics

System and method for providing alignment mark for high-k metal gate process

InventorID:

6248091 ⎘