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Inventor profile of:

Michael Burstein

City:

Cupertino, California

Country:

United States

Published Applications:

8

Last publication date:

2013-10-01

Top Assignees for applications by Michael Burstein

The entities that hold a legal rights for patent applications filed by inventor Burstein Michael:

  • Golden Gate Technology, Inc. 7 San Jose, CA United States
  • GG Technology, Inc. 1 San Jose, CA United States

Recent patent applications by Burstein Michael

Michael Burstein from Cupertino, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2013-10-01
US13149230
-

Methods and software for determining net bounds for placing and routing

#2 | 2013-06-18
US13149258
-

Methods of automatically placing and routing for timing improvement

#3 | 2013-02-05
US13149275
-

Methods and software for placement improvement based on global routing

#4 | 2011-12-01
US20110291769A1
Physics

Method for matching timing on high fanout signal paths using routing guides

#5 | 2011-09-06
US10946926
-

Method for matching timing on high fanout signal paths using routing guides

#6 | 2011-08-02
US11093713
-

Method of placing and routing for power optimization and timing closure

#7 | 2008-04-15
US10946925
-

Method for circuit block placement and circuit block arrangement based on switching activity

#8 | 2007-08-21
US10946688
-

Method for circuit block routing based on switching activity

InventorID:

6253228 ⎘

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