San Jose, California
United States
80
2024-05-02
The entities that hold a legal rights for patent applications filed by inventor Marrow Marcus:
Marcus Marrow from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MAGNETORESISTIVE ASYMMETRY COMPENSATION
#2 | 2022-12-15Synchronous writing of patterned media
#3 | 2022-11-08Storage device that switches detector configuration sets between decoding iterations
#4 | 2022-10-18Synchronous writing of patterned media
#5 | 2022-09-08One-shot state transition probability encoder and decoder
#6 | 2022-08-04Magnetoresistive asymmetry compensation
#7 | 2022-08-04Magnetoresistive asymmetry compensation
#8 | 2022-05-24Hardware-based read sample averaging
#9 | 2022-03-01Magnetoresistive asymmetry compensation
#10 | 2022-02-24One-shot state transition probability encoder and decoder
#11 | 2022-02-03Decoding policy management to support multiple decoding schemes in a single buffer space
#12 | 2021-12-23Concurrent recursive-read averaging and iterative inner and outer code decoding
#13 | 2021-11-09Cancelling adjacent track interference
#14 | 2020-10-13Hardware-based read sample averaging
#15 | 2020-09-29Constrained receiver parameter optimization
#16 | 2020-06-23Preamble defect detection and mitigation
#17 | 2020-06-23Target parameter adaptation
#18 | 2020-03-31Iterative recovery from baseline or timing disturbances
#19 | 2020-03-31Head delay calibration and tracking in MSMR systems
#20 | 2020-03-24Position error signal burst demodulation
#21 | 2020-02-27Data path dynamic range optimization
#22 | 2020-02-11Timing loop for adjacent track interference cancellation
#23 | 2020-01-02Multi-signal realignment for changing sampling clock
#24 | 2019-12-31Disc locked clock-based servo timing
#25 | 2019-12-03Data path dynamic range optimization
#26 | 2019-11-19Loop consistency using multiple channel estimates
#27 | 2019-11-05Cancelling adjacent track interference
#28 | 2019-11-05Regularized parameter adaptation
#29 | 2019-10-29Cancelling adjacent track interference signal with different data rate
#30 | 2019-09-10Multi-stage MISO circuit for fast adaptation
#31 | 2019-08-13Constrained receiver parameter optimization
#32 | 2019-05-21Wide frequency range clock generation with phase interpolation
#33 | 2019-05-21Servo sector detection
#34 | 2019-04-30Preamble defect detection and mitigation
#35 | 2019-04-09MISO equalization with ADC averaging
#36 | 2019-03-26Preamble detection and frequency offset determination
#37 | 2019-01-08Multi-signal realignment for changing sampling clock
#38 | 2018-12-25Timing excursion recovery
#39 | 2018-12-20Approximated parameter adaptation
#40 | 2018-12-20Sampling for multi-reader magnetic recording
#41 | 2018-12-20Hybrid timing recovery
#42 | 2018-12-20Parallelized writing of servo RRO/ZAP fields
#43 | 2018-12-11Target parameter adaptation
#44 | 2018-09-25Iterative recovery from baseline or timing disturbances
#45 | 2018-09-04Multi-stage MISO circuit for fast adaptation
#46 | 2018-07-03Head delay calibration and tracking in MSMR systems
#47 | 2018-06-12Loop consistency using multiple channel estimates
#48 | 2018-05-22Position error signal burst demodulation
#49 | 2018-04-24Wide frequency range clock generation with phase interpolation
#50 | 2018-03-27MISO equalization with ADC averaging
#51 | 2017-11-14Preamble detection and frequency offset determination
#52 | 2017-02-14Decoding of turbo product codes using miscorrection detection
#53 | 2016-09-29Error detection using a logical address key
#54 | 2016-09-08Encoder and decoder design for near-balanced codes
#55 | 2016-07-05Error detection using a logical address key
#56 | 2016-06-28Selective copy-back
#57 | 2016-01-19Memory efficient triggers of read disturb checks in solid state storage
#58 | 2015-09-01Fixed-point detector pruning for constrained codes
#59 | 2015-06-04Error recovery for flash memory
#60 | 2015-02-19Error correction capability improvement in the presence of hard bit errors
#61 | 2015-02-19Generating soft read values which optimize dynamic range
#62 | 2015-01-27Generating soft read values which optimize dynamic range
#63 | 2015-01-01Manufacturing testing for LDPC codes
#64 | 2014-12-02Decision directed and non-decision directed low frequency noise cancelation in turbo detection
#65 | 2014-12-02Error correction capability improvement in the presence of hard bit errors
#66 | 2014-11-27Miscorrection detection for error correcting codes using bit reliabilities
#67 | 2014-11-06Margining decoding utilizing soft-inputs
#68 | 2014-10-30Solid state device coding architecture for chipkill and endurance improvement
#69 | 2014-09-18Coding architecture for multi-level NAND flash memory with stuck cells
#70 | 2014-08-21Generation of a composite read based on neighboring data
#71 | 2014-06-19Error recovery for flash memory
#72 | 2014-06-17Solid state device coding architecture for chipkill and endurance improvement
#73 | 2014-06-05Blind and decision directed multi-level channel estimation
#74 | 2014-05-08Turbo-product codes (TPC) with interleaving
#75 | 2014-02-06Data independent error computation and usage with decision directed error computation
#76 | 2014-01-09Error recovery for flash memory
#77 | 2013-11-28Measure of health for writing to locations in flash
#78 | 2013-11-07Blind and decision directed multi-level channel estimation
#79 | 2013-01-31Inter-track interference cancelation in the presence of frequency offset
#80 | 2012-08-16Blind and decision directed multi-level channel estimation
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