Ming-Hsiu LEE

MEMORY STRUCTURE, MANUFACTURING METHOD THEREOF, OPERATING METHOD THEREOF, AND MEMORY ARRAY

TERNARY CONTENT ADDRESSABLE MEMORY AND DECISION GENERATION METHOD FOR THE SAME

HIGH-LEVEL ARCHITECTURE FOR 3D-NAND BASED IN-MEMORY SEARCH

RESERVOIR DEVICE AND RESERVOIR ARRAY

SEMICONDUCTOR BONDED STRUCTURE AND FABRICATING METHOD THEREOF

NON-VOLATILE 3D MEMORY SEARCH ARCHITECTURE

UNIVERSAL MEMORIES FOR IN-MEMORY COMPUTING

MEMORY DEVICE FOR IN-MEMORY COMPUTING

COMPUTING SYSTEM AND METHOD OF OPERATION THEREOF

CAM CELL, CAM DEVICE AND OPERATION METHOD THEREOF, AND METHOD FOR SEARCHING AND COMPARING DATA

Memory device and intelligent operation method thereof

BONDING STRUCTURE, SEMICONDUCTOR CHIP AND FABRICATING METHOD THEREOF

Programmable logic computation in memory

Storage device for generating identity code and identity code generating method

UNIVERSAL MEMORY FOR IN-MEMORY COMPUTING AND OPERATION METHOD THEREOF

IMS memory cell, IMS method and IMS memory device

Ternary content addressable memory and decision generation method for the same

Method for manufacturing memory device

Memory device and computing method thereof

Memory device for in-memory computing

Memory device and method for operating the same

Semiconductor structure and method for manufacturing having the conductive portions isolated from each other by an insulating 2D material

Content-addressable memory and analog content-addressable memory device

Memory device and computing method using the same

Memory device and method for operating the same

IN-MEMORY COMPUTATION DEVICE AND IN-MEMORY COMPUTATION METHOD TO PERFORM MULTIPLICATION OPERATION IN MEMORY CELL ARRAY ACCORDING TO BIT ORDERS

Memory device and operating method thereof

Ternary content addressable memory and decision generation method for the same

MEMORY DEVICE AND COMPUTING METHOD THEREOF

Flash memory and flash memory cell thereof

CAM cell, CAM memory device and operation method thereof

Content-addressable memory and analog content-addressable memory device

Memory device and method for manufacturing the same

CAM cell, CAM device and operation method thereof, and method for searching and comparing data

Memory device with input circuit, output circuit for performing efficient data searching and comparing within large-sized memory array

Multilevel content addressable memory, multilevel coding method of and multilevel searching method

Content-addressable memory and operation method thereof

Storage device for generating identity code and identity code generating method

Three-way switch array structure and switch array substrate based on NVM

Flash memory and flash memory cell thereof

In-memory computation device and in-memory computation method to perform multiplication operation in memory cell array according to bit orders

DATA RECOGNITION APPARATUS AND RECOGNITION METHOD THEREOF

Semiconductor structure and manufacturing method for the same

Ternary content addressable memory and memory cell thereof

Ternary content addressable memory and decision generation method for the same

Memory cell, memory array and operation method using the same

Training algorithm in artificial neural network (ANN) incorporating non-ideal memory device behavior

Semiconductor structure comprising via element and manufacturing method for the same

Random number generator, random number generating circuit, and random number generating method

Memory and operating method thereof

Semiconductor device for performing sum-of-product computation and operating method thereof

Non-volatile memory and reading method thereof

In-memory computing devices for neural networks

Bit cost scalable 3D phase change cross-point memory

Device and method for generating inherent information of integrated circuits for authentication purpose

Semiconductor memory device, chip ID generation method thereof and manufacturing method thereof

Memory device and operating method for resistive memory cell

Semiconductor memory device and method for temperature compensation using temperature-resistance-voltage functions

Timing device and method thereof

Array structure having local decoders in an electronic device

Resistive memory device with ring-shaped metal oxide on top surfaces of ring-shaped metal layer and barrier layer

Method for healing phase-change memory device and applications thereof

Semiconductor structure, resistive random access memory unit structure, and manufacturing method of the semiconductor structure

Resistive memory and associated operation method

Memory structure and operation method therefor

Phase change memory, writing method thereof and reading method thereof

Low temperature transition metal oxide for memory device

Memory and memory managing method

Self-rectified device, method for manufacturing the same, and applications of the same

Conductive bridge resistive memory device and method of manufacturing the same

Semiconductor device and manufacturing method and operating method for the same

Unipolar programmable metallization cell

Dielectric charge trapping memory cells with redundancy

Operating method for memory device and memory array and operating method for the same

Switching device and operating method for the same and memory array

Resistance memory cell and operation method thereof

Three-dimensional array structure for memory devices

Resistive memory and fabricating method thereof

Approach for phase change memory cells targeting different device specifications

Three dimensional memory array adjacent to trench sidewalls

3D MEMORY AND DECODING TECHNOLOGIES

Resistive memory array and method for controlling operations of the same

High-endurance phase change memory devices and methods for operating the same

Memory device and method of operating the same

3D memory array arranged for FN tunneling program and erase

Verification algorithm for metal-oxide resistive memory

Phase change memory cell structure

Phase change memory with fast write characteristics

Phase change memory coding

3D two bit-per-cell NAND flash memory

Three-dimensional memory devices and methods of manufacturing and operating the same

Method for programming a multilevel phase change memory device

Set algorithm for phase change memory cell

Multi-level cell programming of PCM by varying the reset amplitude

PHASE CHANGE STRUCTURE WITH COMPOSITE DOPING FOR PHASE CHANGE MEMORY

Phase change memory cell structure

Phase change memory having one or more non-constant doping profiles

Methods and apparatus for reducing defect bits in phase change memory

Phase change memory having stabilized microstructure and manufacturing method

Phase change memory cells having vertical channel access transistor and memory plane