Poughkeepsie, New York
United States
30
2026-05-28
The entities that hold a legal rights for patent applications filed by inventor BRULEY JOHN:
JOHN BRULEY from Poughkeepsie, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MAGNETIC TUNNEL JUNCTION FREE LAYER OF MULTIPLE MAGNETIC MATERIALS
#2 | 2026-02-26Method for Stripping Organic Material and Residue from Semiconductor Integrated Circuit
#3 | 2025-01-30FREE LAYER IN MAGNETORESISTIVE RANDOM-ACCESS MEMORY
#4 | 2024-10-03MAGNETIC TUNNEL JUNCTION FREE LAYER OF MULTIPLE MATERIALS
#5 | 2024-07-18ORDERED ALLOY MAGNETIC TUNNEL JUNCTION WITH SIMPLIFIED SEED STRUCTURE
#6 | 2023-12-07SPURIOUS JUNCTION PREVENTION VIA IN-SITU ION MILLING
#7 | 2022-04-21Sacrificial material facilitating protection of a substrate in a qubit device
#8 | 2022-02-24Grain size control of superconducting materials in thin films for Josephson junctions
#9 | 2021-12-23Spurious junction prevention via in-situ ion milling
#10 | 2021-11-04Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements
#11 | 2021-06-24Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements
#12 | 2019-12-26CMOS compatible non-filamentary resistive memory stack
#13 | 2019-09-05ReRAM DEVICE RESISTIVITY CONTROL BY OXIDIZED ELECTRODE
#14 | 2019-08-08FERROELECTRIC DEVICES FREE OF EXTENDED GRAIN BOUNDARIES
#15 | 2019-05-23Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements
#16 | 2019-02-28Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements
#17 | 2018-06-21Shallow, abrupt and highly activated tin extension implant junction
#18 | 2018-03-08Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements
#19 | 2017-10-26STRUCTURES AND METHODS FOR EQUIVALENT OXIDE THICKNESS SCALING ON SILICON GERMANIUM CHANNEL OR III-V CHANNEL OF SEMICONDUCTOR DEVICE
#20 | 2017-10-26Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device
#21 | 2017-01-24Method of producing an un-distorted dark field strain map at high spatial resolution through dark field electron holography
#22 | 2016-07-07High germanium content silicon germanium fins
#23 | 2016-03-10High germanium content silicon germanium fins
#24 | 2014-02-13Reliable physical unclonable function for device authentication
#25 | 2006-07-20On-chip Cu interconnection using 1 to 5 nm thick metal cap
#26 | 2006-03-21Electron holography method
#27 | 2005-03-31Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi
#28 | 2005-03-24Site-specific methodology for localization and analyzing junction defects in mosfet devices
#29 | 2005-03-10CAPACITOR AND FABRICATION METHOD USING ULTRA-HIGH VACUUM CVD OF SILICON NITRIDE
#30 | 2005-03-03Electron microscope magnification standard providing precise calibration in the magnification range 5000X-2000,000X
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