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Inventor profile of:

Terry Borer

City:

Toronto

Country:

Canada

Published Applications:

20

Last publication date:

2017-11-23

Top Assignees for applications by Terry Borer

The entities that hold a legal rights for patent applications filed by inventor Borer Terry:

Recent patent applications by Borer Terry

Terry Borer from Toronto, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2017-11-23
US20170337318A1
Physics

Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices

 #2 | 2015-09-01
US14052210
Physics

Method and apparatus for performing compilation using multiple design flows

 #3 | 2014-02-13
US20140047405A1
Physics

Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices

 #4 | 2013-11-19
US13545320
-

M/A for performing incremental compilation using top-down and bottom-up design approaches

 #5 | 2013-11-19
US11657301
-

Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices

 #6 | 2013-02-05
US12157809
-

Method and apparatus for compiling intellectual property systems design cores using an incremental compile design flow

 #7 | 2012-08-21
US12592960
-

Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches

 #8 | 2011-10-11
US12116136
-

Directed design space exploration

 #9 | 2010-02-23
US11515561
-

Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches

 #10 | 2009-09-22
US11610392
-

Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage

 #11 | 2009-09-22
US10679593
-

Method and apparatus for performing layout-driven optimizations on field programmable gate arrays

 #12 | 2008-12-09
US11384962
-

Method and apparatus for performing incremental compilation

 #13 | 2008-07-15
US11148588
-

Method and apparatus for performing compound duplication of components on field programmable gate arrays

 #14 | 2008-06-17
US10840206
-

Techniques for editing circuit design files to be compatible with a new programmable IC

 #15 | 2008-05-06
US11187076
-

Directed design space exploration

 #16 | 2008-04-15
US10876709
-

Method and apparatus for performing retiming on field programmable gate arrays

 #17 | 2007-10-30
US10903252
-

Leveraging combinations of synthesis, placement and incremental optimizations

 #18 | 2007-08-14
US10806617
-

Method and apparatus for performing logic replication in field programmable gate arrays

 #19 | 2007-08-07
US11040323
-

Synthesis aware placement: a novel approach that combines knowledge of possible resynthesis

 #20 | 2007-02-20
US10625505
-

Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
InventorID:

653656 ⎘