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Inventor profile of:

Gabriel Quan

City:

Toronto

Country:

Canada

Published Applications:

19

Last publication date:

2023-10-19

Top Assignees for applications by Gabriel Quan

The entities that hold a legal rights for patent applications filed by inventor Quan Gabriel:

Recent patent applications by Quan Gabriel

Gabriel Quan from Toronto, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-10-19
US20230333826A1
Physics

FAST FPGA COMPILATION THROUGH BITSTREAM STITCHING

 #2 | 2023-07-27
US20230237231A1
Physics

Modular Compilation Flows for a Programmable Logic Device

 #3 | 2020-08-13
US20200257839A1
Physics

Method and apparatus for performing fast incremental physical design optimization

 #4 | 2020-04-28
US15379747
Physics

Method and apparatus for performing fast incremental physical design optimization

 #5 | 2017-11-23
US20170337318A1
Physics

Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices

 #6 | 2017-02-14
US14200897
Physics

Method and apparatus for performing fast incremental physical design optimization

 #7 | 2015-09-01
US14052210
Physics

Method and apparatus for performing compilation using multiple design flows

 #8 | 2014-02-13
US20140047405A1
Physics

Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices

 #9 | 2013-11-19
US13545320
-

M/A for performing incremental compilation using top-down and bottom-up design approaches

 #10 | 2013-11-19
US11657301
-

Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices

 #11 | 2013-04-30
US12968128
-

Specifying placement and routing constraints for security and redundancy

 #12 | 2012-08-21
US12592960
-

Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches

 #13 | 2010-02-23
US11515561
-

Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches

 #14 | 2009-09-22
US10679593
-

Method and apparatus for performing layout-driven optimizations on field programmable gate arrays

 #15 | 2008-12-09
US11384962
-

Method and apparatus for performing incremental compilation

 #16 | 2008-04-15
US10876709
-

Method and apparatus for performing retiming on field programmable gate arrays

 #17 | 2007-08-14
US10806617
-

Method and apparatus for performing logic replication in field programmable gate arrays

 #18 | 2007-03-20
US10618416
-

Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices

 #19 | 2007-02-20
US10868625
-

Method and apparatus for placement of components onto programmable logic devices
InventorID:

653657 ⎘