Toronto
Canada
21
2017-11-23
The entities that hold a legal rights for patent applications filed by inventor Brown Stephen D.:
Stephen D. Brown from Toronto, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices
#2 | 2017-03-07Method and apparatus for performing multiple stage physical synthesis
#3 | 2015-09-01Method and apparatus for performing compilation using multiple design flows
#4 | 2014-10-07Method and apparatus for performing multiple stage physical synthesis
#5 | 2014-02-13Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices
#6 | 2013-11-19M/A for performing incremental compilation using top-down and bottom-up design approaches
#7 | 2013-11-19Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices
#8 | 2013-08-13Method and apparatus for performing multiple stage physical synthesis
#9 | 2012-10-23Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis
#10 | 2012-08-21Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
#11 | 2012-01-10Methods for instruction trace decomposition
#12 | 2011-08-09Method and apparatus for performing multiple stage physical synthesis
#13 | 2010-02-23Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
#14 | 2009-11-17Method and apparatus for performing post-placement routability optimization
#15 | 2009-09-22Method and apparatus for performing layout-driven optimizations on field programmable gate arrays
#16 | 2009-03-03Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines
#17 | 2008-12-09Method and apparatus for performing incremental compilation
#18 | 2008-01-08Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arrays
#19 | 2007-03-27Method and apparatus for designing systems using logic regions
#20 | 2007-03-20Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices
#21 | 2007-02-20Method and apparatus for placement of components onto programmable logic devices
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