Radebeul
Germany
41
2023-03-02
The entities that hold a legal rights for patent applications filed by inventor Richter Ralf:
Ralf Richter from Radebeul, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Ferroelectric nonvolatile memory device and integration schemes
#2 | 2018-12-25Ferro-FET device with buried buffer/ferroelectric layer stack
#3 | 2018-12-20Transistor element including a buried insulating layer having enhanced functionality
#4 | 2018-11-08Non-volatile transistor element including a buried ferroelectric material based storage mechanism
#5 | 2018-07-24Programmable logic elements and methods of operating the same
#6 | 2018-06-07Logic and flash field-effect transistors
#7 | 2018-06-07Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell
#8 | 2018-04-19Flash memory device
#9 | 2018-02-15Semiconductor device comprising a floating gate flash memory device
#10 | 2018-01-16Flash memory device
#11 | 2017-12-12Method of forming a semiconductor device structure and semiconductor device structure
#12 | 2017-11-16Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and method for the formation thereof
#13 | 2017-11-02Method of forming a capacitor structure and capacitor structure
#14 | 2017-05-25Memory device structure
#15 | 2017-04-27Method of forming a memory device structure and memory device structure
#16 | 2016-10-27CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH
#17 | 2016-10-13DENSELY PACKED TRANSISTOR DEVICES
#18 | 2016-09-15Three-dimensional transistor with improved channel mobility
#19 | 2016-08-11Methods of forming a complex GAA FET device at advanced technology nodes
#20 | 2016-06-09Method of forming a semiconductor device structure and such a semiconductor device structure
#21 | 2016-04-28Multi-gate FETs having corrugated semiconductor stacks and method of forming the same
#22 | 2016-03-10FINFET doping method with curvilnear trajectory implantation beam path
#23 | 2016-03-03INTEGRATED CIRCUITS WITH A BOWED SUBSTRATE, AND METHODS FOR PRODUCING THE SAME
#24 | 2016-01-07INTEGRATED CIRCUIT PRODUCT COMPRISED OF MULTIPLE P-TYPE SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES
#25 | 2015-09-08Integrated inductor
#26 | 2015-07-30LOW LEAKAGE PMOS TRANSISTOR
#27 | 2015-04-16Three-dimensional transistor with improved channel mobility
#28 | 2015-03-19INTEGRATED CIRCUITS WITH A CORRUGATED GATE, AND METHODS FOR PRODUCING THE SAME
#29 | 2014-12-04Spacer stress relaxation
#30 | 2014-09-18Methods for fabricating integrated circuits with semiconductor substrate protection
#31 | 2014-09-18Integrated circuits and methods for fabricating integrated circuits with gate electrode structure protection
#32 | 2014-09-18SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR HAVING A LAYER OF A STRESS-CREATING MATERIAL AND METHOD FOR THE FORMATION THEREOF
#33 | 2014-09-18HK/MG process flows for P-type semiconductor devices
#34 | 2014-09-18Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment
#35 | 2014-09-11Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material
#36 | 2014-09-11Method for forming a semiconductor device and semiconductor device structures
#37 | 2014-09-11Contact geometry having a gate silicon length decoupled from a transistor length
#38 | 2014-09-04STRESS MEMORIZATION TECHNIQUE
#39 | 2014-09-04Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe
#40 | 2014-05-27Semiconductor device structure and methods for forming a CMOS integrated circuit structure
#41 | 2014-02-20Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress
655608 ⎘