Slingerlands, New York
United States
29
2020-03-12
The entities that hold a legal rights for patent applications filed by inventor DORIS BRUCE:
BRUCE DORIS from Slingerlands, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Device with integration of light-emitting diode, light sensor, and bio-electrode sensors on a substrate
#2 | 2020-02-06Device with integration of light-emitting diode, light sensor, and bio-electrode sensors on a substrate
#3 | 2018-04-05Fabrication of silicon germanium-on-insulator FinFET
#4 | 2018-01-04FORMING A SILICON BASED LAYER IN A TRENCH TO PREVENT CORNER ROUNDING
#5 | 2017-06-22Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
#6 | 2017-06-15Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
#7 | 2016-12-29Fabrication of silicon germanium-on-insulator finFET
#8 | 2016-12-01Methods of forming replacement fins for a FinFET device using a targeted thickness for the patterned fin etch mask
#9 | 2016-10-06FinFET device having a high germanium content fin structure and method of making same
#10 | 2016-09-08Fin isolation structures facilitating different fin isolation schemes
#11 | 2016-09-01Methods of modulating strain in PFET and NFET FinFET semiconductor devices
#12 | 2016-08-04Methods of forming fin isolation regions on FinFET semiconductor devices using an oxidation-blocking layer of material and by performing a fin-trimming process
#13 | 2016-08-04Methods of forming fin isolation regions on FinFET semiconductor devices by implantation of an oxidation-retarding material
#14 | 2016-06-30Silicon germanium-on-insulator FinFET
#15 | 2016-06-23FinFET device having a high germanium content fin structure and method of making same
#16 | 2016-05-24Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of material
#17 | 2016-05-10Virtual relaxed substrate on edge-relaxed composite semiconductor pillars
#18 | 2016-04-26Methods of forming replacement fins for a FinFET device
#19 | 2016-03-15Method for single fin cuts using selective ion implants
#20 | 2016-01-14Low leakage dual STI integrated circuit including FDSOI transistors
#21 | 2016-01-14Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same
#22 | 2015-09-10Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device
#23 | 2015-07-16Methods of forming isolated germanium-containing fins for a FinFET semiconductor device
#24 | 2014-12-04Method for the formation of a protective dual liner for a shallow trench isolation structure
#25 | 2014-12-04Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
#26 | 2014-12-04Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
#27 | 2014-10-02Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods
#28 | 2014-10-02Memory device having multiple dielectric gate stacks and related methods
#29 | 2014-02-27Isolation regions for SOI devices
663106 ⎘