Paul A. Grudowski

Gate security feature

Semiconductor device including an active region and two layers having different stress characteristics

MULTILAYER SILICON NITRIDE DEPOSITION FOR A SEMICONDUCTOR DEVICE

Process of forming an electronic device including insulating layers having different strains

Fabrication of a semiconductor device with stressor

Method of forming a via

Disposable organic spacers

Method of making a semiconductor device with embedded stressor

Electronic device including a transistor structure having an active region adjacent to a stressor layer

SEMICONDUCTOR DEVICE WITH STRESSORS AND METHODS THEREOF

Method of forming a semiconductor device with multiple tensile stressor layers

Electronic device including insulating layers having different strains

Multilayer silicon nitride deposition for a semiconductor device

Multilayer silicon nitride deposition for a semiconductor device

Anneal of epitaxial layer in a semiconductor device

Semiconductor device including an active region and two layers having different stress characteristics

METHOD FOR FORMING A STRESSOR LAYER

Stressor integration and method thereof

Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility

Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors

Method for improving self-aligned silicide extendibility with spacer recess using a stand-alone recess etch integration

Semiconductor device having stressors and method for forming

Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device

Process for forming an electronic device including transistor structures with sidewall spacers

Method of forming an interlayer dielectric

Method of forming an electronic device

Method of making a nitrided gate dielectric

Differentially nitrided gate dielectrics in CMOS fabrication process

Transistor sidewall spacer stress modulation

Integrated circuit device and method therefor

Semiconductor fabrication process using transistor spacers of differing widths

Transistor sidewall spacer stress modulation

Integrated circuit device and method therefor