Inventor profile of:

Joseph Tzou

City:

Mountain View, California

Country:

United States

Published Applications:

17

Last publication date:

2026-06-18

Top Assignees for applications by Joseph Tzou

The entities that hold a legal rights for patent applications filed by inventor Tzou Joseph:

Recent patent applications by Tzou Joseph

Joseph Tzou from Mountain View, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-06-18
US20260172034A1
Electricity

PROGRAMMABLE ELEMENT ARRAY

#2 | 2017-05-02
US14866260
Physics

Access methods and circuits for memory devices having multiple channels and multiple banks

#3 | 2014-11-20
US20140340978A1
Physics

Access methods and circuits for memory devices having multiple banks

#4 | 2014-10-28
US13795134
Physics

Data forwarding circuits and methods for memory devices with write latency

#5 | 2014-02-27
US20140056093A1
Physics

Access methods and circuits for memory devices having multiple banks

#6 | 2013-09-03
US13717637
-

Memory device data latency circuits and methods

#7 | 2012-01-19
US20120014202A1
Physics

Memory device and method

#8 | 2010-05-18
US11963446
-

Memory having read disturb test mode

#9 | 2010-04-29
US20100103762A1
Physics

Memory device and method

#10 | 2010-04-01
US20100082861A1
Physics

Memory system and method

#11 | 2010-03-23
US11958215
-

Area efficient and fast static random access memory circuit and method

#12 | 2009-04-02
US20090085614A1
Electricity

Circuits and methods for programming integrated circuit input and output impedances

#13 | 2008-07-22
US11237378
-

Single late-write for standard synchronous SRAMs

#14 | 2007-09-11
US10785826
-

Method and apparatus for built-in self-test (BIST) of integrated circuit device

#15 | 2007-03-27
US10927583
-

Memory array with current limiting device for preventing particle induced latch-up

#16 | 2006-12-05
US10124773
-

Hiding refresh in 1T-SRAM architecture

#17 | 2006-11-28
US10871825
-

Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses

InventorID:

664674 ⎘