Paul Gilbert Meyer

Matrix multiplication packing with instruction reordering

Interconnect mode for computational arrays

Vector engine for efficient beam search

Tile assignment for matrix multiplication packing

Reducing power consumption in integrated circuits

Flexible array data loading

Throughput increase for compute engine

Configurable vector compute engine

Fine-grained sparsity computations in systolic array

Increasing performance of computational array accelerators

Emulating fine-grained sparsity in a systolic array

Throughput increase for tensor operations

Resizable scratchpad memory

Programmable vector engine for efficient beam search

Programmable compute engine having transpose operations

Machine instructions for decoding acceleration including fuse input instructions to fuse multiple JPEG data blocks together to take advantage of a full SIMD width of a processor