Inventor profile of:

Vinod Chamarty

City:

Campbell, California

Country:

United States

Published Applications:

11

Last publication date:

2026-02-26

Top Assignees for applications by Vinod Chamarty

The entities that hold a legal rights for patent applications filed by inventor Chamarty Vinod:

Recent patent applications by Chamarty Vinod

Vinod Chamarty from Campbell, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-02-26
US20260057198A1
Physics

BROADCASTING POWER LIMITING MANAGEMENT RESPONSES IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP

#2 | 2024-12-26
US20240428024A1
Physics

BROADCASTING POWER LIMITING MANAGEMENT RESPONSES IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP

#3 | 2024-12-26
US20240427411A1
Physics

HIERARCHICAL POWER ESTIMATION AND THROTTLING IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP

#4 | 2024-12-26
US20240427410A1
Physics

HIERARCHICAL POWER ESTIMATION AND THROTTLING IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP

#5 | 2024-12-26
US20240427400A1
Physics

Integrated circuits (IC) chips including throttle request accumulate circuits for controlling power consumed in processing circuits and related methods

#6 | 2024-12-26
US20240427397A1
Physics

INTEGRATED CIRCUITS (IC) CHIPS INCLUDING THROTTLE REQUEST ACCUMULATE CIRCUITS FOR CONTROLLING POWER CONSUMED IN PROCESSING CIRCUITS AND RELATED METHODS

#7 | 2024-12-26
US20240427393A1
Physics

TIME SYNCHRONIZATION OF COLLECTING AND REPORTING POWER EVENTS BETWEEN HIERARCHICAL POWER THROTTLING CIRCUITS IN A HIERARCHICAL POWER MANAGEMENT SYSTEM

#8 | 2024-12-26
US20240427392A1
Physics

TIME SYNCHRONIZATION OF COLLECTING AND REPORTING POWER EVENTS BETWEEN HIERARCHICAL POWER THROTTLING CIRCUITS IN A HIERARCHICAL POWER MANAGEMENT SYSTEM

#9 | 2024-10-31
US20240362103A1
Physics

DETECTING AND RECOVERING FROM TIMEOUTS IN SCALABLE MESH NETWORKS IN PROCESSOR-BASED DEVICES

#10 | 2024-09-26
US20240320125A1
Physics

TRACING CIRCUIT INCLUDING MEMORY MAPPED TRACE BUFFERS IN NODES OF A MESH NETWORK

#11 | 2024-06-20
US20240202087A1
Physics

ROUTING RAW DEBUG DATA USING TRACE INFRASTRUCTURE IN PROCESSOR-BASED DEVICES

InventorID:

6694979 ⎘