Dresden
Germany
35
2018-11-08
The entities that hold a legal rights for patent applications filed by inventor Illgen Ralf:
Ralf Illgen from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Non-volatile transistor element including a buried ferroelectric material based storage mechanism
#2 | 2018-02-08Semiconductor-on-insulator wafer, semiconductor structure including a transistor, and methods for the formation and operation thereof
#3 | 2017-11-23SEMICONDUCTOR DEVICE AND METHOD
#4 | 2017-07-13Semiconductor structure including a first transistor and a second transistor
#5 | 2017-01-26Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistor
#6 | 2016-12-08Ferroelectric FinFET
#7 | 2016-09-08Ferroelectric FinFET
#8 | 2016-03-10ROBUST POST-GATE SPACER PROCESSING AND DEVICE
#9 | 2016-03-03Temperature independent resistor
#10 | 2015-07-30ULTRATHIN BODY FULLY DEPLETED SILICON-ON-INSULATOR INTEGRATED CIRCUITS AND METHODS FOR FABRICATING SAME
#11 | 2014-12-11Device including a transistor having a stressed channel region and method for the formation thereof
#12 | 2014-09-04TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES FORMED IN A SILICON/GERMANIUM SUBSTRATE
#13 | 2014-07-24Method of forming a semiconductor structure including a vertical nanowire
#14 | 2014-05-15Source and drain doping using doped raised source and drain regions
#15 | 2014-05-01THREE-DIMENSIONAL SILICON-BASED TRANSISTOR COMPRISING A HIGH-MOBILITY CHANNEL FORMED BY NON-MASKED EPITAXY
#16 | 2014-01-30METHODS FOR FABRICATING HIGH CARRIER MOBILITY FINFET STRUCTURES
#17 | 2014-01-30Threshold voltage adjustment in a fin transistor by corner implantation
#18 | 2014-01-16Replacement gate FinFET structures with high mobility channel
#19 | 2013-12-26Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same
#20 | 2013-10-24Integrated circuits having protruding source and drain regions and methods for forming integrated circuits
#21 | 2013-09-19METHODS OF FORMING FEATURES ON AN INTEGRATED CIRCUIT PRODUCT USING A NOVEL COMPOUND SIDEWALL IMAGE TRANSFER TECHNIQUE
#22 | 2013-08-01Methods for fabricating MOS devices with stress memorization
#23 | 2013-07-18Strain engineering in three-dimensional transistors based on strained isolation material
#24 | 2013-07-11In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices
#25 | 2013-07-11STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR FABRICATION
#26 | 2013-03-21CMOS SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS
#27 | 2013-02-28Methods of forming stressed silicon-carbon areas in an NMOS transistor
#28 | 2013-02-28Implantation of hydrogen to improve gate insulation layer-substrate interface
#29 | 2013-02-28Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same
#30 | 2013-02-28Threshold voltage adjustment in a Fin transistor by corner implantation
#31 | 2013-02-07N-CHANNEL TRANSISTOR COMPRISING A HIGH-K METAL GATE ELECTRODE STRUCTURE AND A REDUCED SERIES RESISTANCE BY EPITAXIALLY FORMED SEMICONDUCTOR MATERIAL IN THE DRAIN AND SOURCE AREAS
#32 | 2013-01-31Methods of forming a PMOS device with in situ doped epitaxial source/drain regions
#33 | 2012-09-13METHODS FOR FABRICATING CMOS INTEGRATED CIRCUITS HAVING METAL SILICIDE CONTACTS
#34 | 2012-06-14Technique for enhancing dopant profile and channel conductivity by millisecond anneal processes
#35 | 2011-05-26Technique for enhancing dopant profile and channel conductivity by millisecond anneal processes
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