Fairview, Texas
United States
30
2021-07-22
The entities that hold a legal rights for patent applications filed by inventor Wise Rick L.:
Rick L. Wise from Fairview, US has applied for patents for these inventions. The list has both pending applications and granted patents:
HIGH MOBILITY TRANSISTORS
#2 | 2019-04-04High mobility transistors
#3 | 2017-02-02High mobility transistors
#4 | 2016-08-04High mobility transistors
#5 | 2016-07-14HIGH MOBILITY TRANSISTORS
#6 | 2015-10-15Temperature compensated bulk acoustic wave resonator with a high coupling coefficient
#7 | 2015-08-27MECHANICALLY ROBUST SILICON SUBSTRATE HAVING GROUP IIIA-N EPITAXIAL LAYER THEREON
#8 | 2015-07-02High mobility transistors
#9 | 2015-07-02High mobility transistors
#10 | 2015-07-02METHOD TO IMPROVE SLIP RESISTANCE OF SILICON WAFERS
#11 | 2015-04-30CZOCHRALSKI SUBSTRATES HAVING REDUCED OXYGEN DONORS
#12 | 2015-01-15Integrated circuits with aligned (100) NMOS and (110) PMOS finFET sidewall channels
#13 | 2014-11-20Ultrashallow emitter formation using ALD and high temperature short time annealing
#14 | 2014-11-06Layer transfer of silicon onto III-nitride material for heterogenous integration
#15 | 2014-02-13Accelerated furnace ramp rates for reduced slip
#16 | 2014-02-06Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels
#17 | 2013-03-14EXTENDED AREA COVER PLATE FOR INTEGRATED INFRARED SENSOR
#18 | 2013-01-31Reduction of STI corner defects during SPE in semiconductor device fabrication using DSB substrate and hot technology
#19 | 2012-07-12Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels
#20 | 2011-06-23Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels
#21 | 2011-03-10Ultrashallow emitter formation using ALD and high temperature short time annealing
#22 | 2010-12-02REDUCTION OF STI CORNER DEFECTS DURING SPE IN SEMICONDCUTOR DEVICE FABRICATION USING DSB SUBSTRATE AND HOT TECHNOLOGY
#23 | 2009-03-05METHOD TO REDUCE RESIDUAL STI CORNER DEFECTS GENERATED DURING SPE IN THE FABRICATION OF NANO-SCALE CMOS TRANSISTORS USING DSB SUBSTRATE AND HOT TECHNOLOGY
#24 | 2008-12-18Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrate
#25 | 2008-12-11Semiconductor device made by the method of producing hybrid orientnation (100) strained silicon with (110) silicon
#26 | 2008-08-07Trench Isolation Structure and a Method of Manufacture Therefor
#27 | 2008-06-05Semiconductor Device Manufactured Using Passivation of Crystal Domain Interfaces in Hybrid Orientation Technology
#28 | 2007-04-19Trench isolation structure having an implanted buffer layer
#29 | 2005-12-22Trench isolation structure and a method of manufacture therefor
#30 | 2005-12-22Method of manufacture for a trench isolation structure having an implanted buffer layer
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