Inventor profile of:

Gregory S. Spencer

City:

Pflugerville, Texas

Country:

United States

Published Applications:

20

Last publication date:

2013-11-28

Top Assignees for applications by Gregory S. Spencer

The entities that hold a legal rights for patent applications filed by inventor Spencer Gregory S.:

Recent patent applications by Spencer Gregory S.

Gregory S. Spencer from Pflugerville, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2013-11-28
US20130313668A1
Physics

PHOTRONIC DEVICE WITH REFLECTOR AND METHOD FOR FORMING

#2 | 2013-01-31
US20130029485A1
Electricity

Method of making a die with recessed aluminum die pads

#3 | 2012-04-05
US20120080730A1
Physics

Semiconductor device with photonics

#4 | 2011-09-15
US20110223706A1
Electricity

METHOD OF FORMING A PHOTODETECTOR

#5 | 2011-02-03
US20110027950A1
Electricity

METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A PHOTODETECTOR

#6 | 2011-01-18
US12543619
-

Method of making a vertical photodetector

#7 | 2010-11-04
US20100276735A1
Physics

Semiconductor device with photonics

#8 | 2010-09-16
US20100230756A1
Electricity

Semiconductor device with selectively modulated gate work function

#9 | 2008-12-04
US20080299750A1
Electricity

Multiple millisecond anneals for semiconductor device fabrication

#10 | 2008-11-06
US20080274595A1
Electricity

Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation

#11 | 2008-11-06
US20080274594A1
Electricity

Step height reduction between SOI and EPI for DSO and BOS integration

#12 | 2008-10-30
US20080268587A1
Electricity

Inverse slope isolation and dual surface orientation integration

#13 | 2008-10-23
US20080258219A1
Electricity

Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer

#14 | 2008-07-10
US20080163813A1
Electricity

Anneal of epitaxial layer in a semiconductor device

#15 | 2008-01-31
US20080026599A1
Electricity

Transfer of stress to a layer

#16 | 2007-12-27
US20070298623A1
Electricity

METHOD FOR STRAINING A SEMICONDUCTOR DEVICE

#17 | 2007-09-20
US20070218659A1
Electricity

Selective silicon deposition for planarized dual surface orientation integration

#18 | 2007-09-20
US20070218654A1
Electricity

Silicon deposition over dual surface orientation substrates to promote uniform polishing

#19 | 2005-06-16
US20050130405A1
Electricity

Method of making a semiconductor device having a low K dielectric

#20 | 2005-03-17
US20050059245A1
Electricity

Integration of ultra low K dielectric in a semiconductor fabrication process

InventorID:

67290 ⎘