Jay William Strane

STACKED FET WITH FLEXIBLE INTER-EPI DIELECTRIC THICKNESS

MONOLITHIC STACKED COMPLEMENTARY TRANSISTOR STRUCTURES WITH DUAL WORK FUNCTION METAL GATES

MONOLITHIC STACKED COMPLEMENTARY TRANSISTOR STRUCTURES WITH DUAL WORK FUNCTION METAL GATES

SHAPED EPITAXY

DIELECTRIC INNER SPACERS FOR NANOSHEET TRANSISTORS

STACKED TRANSISTOR FRONTSIDE CONTACT FORMATION

STACKED FIELD EFFECT TRANSISTOR WITH EPITAXY CUT FOR SOURCE/DRAIN CONTACT

SEMICONDUCTOR DEVICE WITH STACKED DEVICE TYPES

LATERAL PASSIVE DIODES CO-INTEGRATED WITH NANOSHEET TECHNOLOGY

CO-INTEGRATION OF PASSIVE DEVICE AND VERTICALLY STACKED NANOSHEETS

U-SHAPED SPACER TO PROTECT THE INTRA-DEVICE SPACE REGION FOR STACKED FET

STACKED FIELD-EFFECT TRANSISTOR DEVICE WITH BACKSIDE CUT FOR TOP SOURCE/DRAIN ACCESS

ENLARGED BOTTOM CONTACT AREA IN STACKED TRANSISTORS

FIELD-EFFECT TRANSISTOR CRESCENT-SHAPED DIELECTRIC ISOLATION

DUAL SIDED CIRCUIT CONNECTIONS

LOCAL TRAPPED METAL CONTACT FOR STACKED FET

STACKED FET WITH BOTTOM EPI SIZE CONTROL AND WRAPAROUND BACKSIDE CONTACT

SHARED SOURCE/DRAIN CONTACT FOR STACKED TRANSISTORS

MERGED SELF-ALIGNED BACKSIDE CONTACT

PLACEHOLDER PROFILE FORMATION FOR BACKSIDE CONTACT

BACKSIDE CONTACTS FOR SOURCE/DRAIN REGIONS

ASYMMETRIC GATE EXTENSION IN STACKED FET

AIR POCKET BETWEEN TOP AND BOTTOM SOURCE/DRAIN REGIONS

FRONTSIDE TO BACKSIDE SIGNAL VIA IN EDGE CELL