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Inventor profile of:

Chen-Nan Yeh

City:

Hsi-Chih

Country:

Taiwan

Published Applications:

Last publication date:

2015-10-08

Top Assignees for applications by Chen-Nan Yeh

The entities that hold a legal rights for patent applications filed by inventor Yeh Chen-Nan:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 26 Hsin-Chu, Taiwan
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 2 Hsin-Chu, Taiwan
Taiwan Semiconductor Manufacturing Comapny, Ltd. 1 Hsin-Chu, Taiwan
Taiwan Semiconductor Manufacturing Company, Ltd. 1 Hin-Chu, Taiwan
Taiwan Semiconductor Manufacturing Company, Ltd. Hsin-Chu, Taiwan 1 Hsin-Chu, Taiwan

Recent patent applications by Yeh Chen-Nan

Chen-Nan Yeh from Hsi-Chih, TW has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2015-10-08

US20150287784A1

Electricity

Reducing resistance in source and drain regions of FinFETs

#2 | 2015-09-17

US20150262861A1

Electricity

Dielectric punch-through stoppers for forming FinFETs having dual Fin heights

#3 | 2014-03-13

US20140070318A1

Electricity

Reducing resistance in source and drain regions of FinFETs

#4 | 2012-11-29

US20120299110A1

Electricity

Dielectric punch-through stoppers for forming FinFETs having dual fin heights

#5 | 2012-08-23

US20120211807A1

Electricity

System and method for source/drain contact processing

#6 | 2012-04-19

US20120094464A1

Electricity

Method of fabricating semiconductor device isolation structure

#7 | 2012-04-05

US20120083107A1

Electricity

FinFETs having dielectric punch-through stoppers

#8 | 2012-02-02

US20120025313A1

Electricity

Germanium FinFETs having dielectric punch-through stoppers

#9 | 2011-09-15

US20110223735A1

Electricity

Reducing resistance in source and drain regions of FinFETs

#10 | 2011-07-14

US20110171805A1

Electricity

System and method for source/drain contact processing

#11 | 2011-04-21

US20110092019A1

Electricity

Method for stacked contact with low aspect ratio

#12 | 2011-02-17

US20110037129A1

Electricity

Semiconductor device having multiple fin heights

#13 | 2010-09-02

US20100221878A1

Electricity

Hybrid metal fully silicided (FUSI) gate

#14 | 2010-07-01

US20100163971A1

Electricity

Dielectric punch-through stoppers for forming FinFETs having dual fin heights

#15 | 2010-06-10

US20100144121A1

Electricity

Germanium FinFETs having dielectric punch-through stoppers

#16 | 2009-11-12

US20090278196A1

Electricity

FinFETs having dielectric punch-through stoppers

#17 | 2009-10-08

US20090253266A1

Electricity

Semiconductor device having multiple fin heights

#18 | 2009-10-08

US20090250769A1

Electricity

Semiconductor device having multiple fin heights

#19 | 2009-04-16

US20090096002A1

Electricity

System and method for source/drain contact processing

#20 | 2009-04-16

US20090095980A1

Electricity

Reducing resistance in source and drain regions of FinFETs

#21 | 2009-04-02

US20090085126A1

Electricity

Hybrid metal fully silicided (FUSI) gate

#22 | 2009-02-05

US20090035909A1

Electricity

Method of fabrication of a FinFET element

#23 | 2008-12-11

US20080303104A1

Electricity

Method of fabricating semiconductor device isolation structure

#24 | 2008-10-30

US20080265338A1

Electricity

Semiconductor device having multiple fin heights

#25 | 2008-10-30

US20080265321A1

Electricity

Fin field-effect transistors

#26 | 2008-08-14

US20080194087A1

Electricity

Polysilicon gate formation by in-situ doping

#27 | 2008-08-14

US20080191352A1

Electricity

Stacked contact with low aspect ratio

#28 | 2007-01-04

US20070004193A1

Electricity

Method for reworking low-k dual damascene photo resist

#29 | 2006-08-10

US20060178008A1

Electricity

Post etch copper cleaning using dry plasma

InventorID:

683052 ⎘