Mahbub Rashed

COMMON BIAS CONTROL FOR DEVICES HAVING UNCORRELATED POWER SUPPLIES

ISOLATION STRUCTURE FOR MULTI-VOLTAGE INTEGRATED CIRCUIT

METHOD AND SYSTEM EMPLOYING LINEAR DISTANCE MARKER-BASED DESIGN LAYOUT ANALYSIS

CELL LAYOUTS

MEMORY STRUCTURE INCLUDING A LOW CELL SUPPLY VOLTAGE PROGRAMMING CIRCUIT

AREA-EFFICIENT FULLY DEPLETED SEMICONDUCTOR-ON-INSULATOR STRUCTURE WITH MIXED THRESHOLD VOLTAGE TRANSISTORS

COMPACT MEMORY-IN-PIXEL DISPLAY STRUCTURE

ANTENNA STRUCTURE

SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION

INTEGRATED CIRCUIT STRUCTURE WITH MULTI-ROW CELL FOR ACCOMMODATING MIXED TRACK HEIGHT

Back bias control for always-on circuit section enabling leakage reduction during power saving mode

STRUCTURE AND METHOD FOR DELAYING OF DATA SIGNAL FROM PULSE LATCH WITH LOCKUP LATCH

INTEGRATED CIRCUIT STRUCTURE WITH CELLS HAVING ASYMMETRIC POWER RAIL

CROSS COUPLE DESIGN FOR HIGH DENSITY STANDARD CELLS

Post-manufacture latch timing control blocks in pipelined processors

LOCAL INTERCONNECT POWER RAILS AND UPPER POWER RAILS

Circuit structure and related method for radiation resistant memory cell

Deep nwell contact structures

Cell layouts

System and method employing power-optimized timing closure

Semiconductor structure including sectioned well region

Low-leakage sense circuit, memory circuit incorporating the low-leakage sense circuit, and method

Single-rail memory circuit with row-specific voltage supply lines and boost circuits

Low clock load dynamic dual output latch circuit

Positive and negative full-range back-bias generator circuit structure

Structure and method for flexible power staple insertion

Electrostatic discharge protection device

Structure and method for flexible power staple insertion

Calibration devices for I/O driver circuits having switches biased differently for different temperatures

On-chip voltage generator for back-biasing field effect transistors in a circuit block

FDSOI semiconductor device with contact enhancement layer and method of manufacturing

POWER RAIL AND MOL CONSTRUCTS FOR FDSOI

Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library

Circuit design having aligned power staples

Special construct for continuous non-uniform active region FinFET standard cells

Method, apparatus, and system for improved memory cell design having unidirectional layout using self-aligned double patterning

Special construct for continuous non-uniform active region FinFET standard cells

Memory bit cell for reduced layout area

Special construct for continuous non-uniform RX FinFET standard cells

Memory bit cell for reduced layout area

Special constructs for continuous non-uniform active region FinFET standard cells

Method and apparatus for assisted metal routing

Wide pin for improved circuit routing

FORMING GATE TIE BETWEEN ABUTTING CELLS AND RESULTING DEVICE

Method and apparatus for modified cell architecture and the resulting device

DENSELY PACKED STANDARD CELLS FOR INTEGRATED CIRCUIT PRODUCTS, AND METHODS OF MAKING SAME

Power rail layout for dense standard cell library

Wide pin for improved circuit routing

Forming modified cell architecture for finFET technology and resulting device

Densely packed standard cells for integrated circuit products, and methods of making same

FinFET device and methods of fabrication

Bit cell with double patterned metal layer structures

Standard cell connection for circuit routing

Methods for improving double patterning route efficiency

Parameterized cell for planar and finFET technology design

Integrating optimal planar and three-dimensional semiconductor design layouts

Variable power rail design

Methods of using a trench salicide routing layer

Cross-coupling-based design using diffusion contact structures

Double patterning compatible colorless M1 route

Bit cell with double patterned metal layer structures