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Inventor profile of:

Jonathan Lane

City:

Sandy, Utah

Country:

United States

Published Applications:

Last publication date:

2026-06-25

Recent patent applications by Lane Jonathan

Jonathan Lane from Sandy, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-06-25

US20260181928A1

Electricity

SEMICONDUCTOR PROCESSING FOR BIPOLAR JUNCTION TRANSISTOR (BJT)

#2 | 2026-04-30

US20260123298A1

Electricity

FACET TRAPPING FOR EPITAXIAL GROWTH

#3 | 2026-04-30

US20260123029A1

Electricity

SEMICONDUCTOR PROCESSING FOR FACET TRAPPING IN EPITAXIAL GROWTH

#4 | 2025-12-04

US20250374657A1

Electricity

SEMICONDUCTOR PROCESSING INTEGRATION FOR BIPOLAR JUNCTION TRANSISTOR (BJT)

#5 | 2025-12-04

US20250374656A1

Electricity

SEMICONDUCTOR PROCESSING INTEGRATION FOR BIPOLAR JUNCTION TRANSISTOR (BJT)

#6 | 2025-09-18

US20250294785A1

Electricity

SEMICONDUCTOR PROCESSING FOR BIPOLAR JUNCTION TRANSISTOR (BJT)

#7 | 2025-07-17

US20250234632A1

Electricity

SEMICONDUCTOR PROCESSING INTEGRATION FOR BIPOLAR JUNCTION TRANSISTOR (BJT)

#8 | 2025-06-26

US20250212404A1

Electricity

INTEGRATED FLASH MEMORY AND COMPLEMENTARY FIELD EFFECT TRANSITOR SEMICONDUCTOR PROCESSING

#9 | 2025-05-29

US20250176201A1

Electricity

SEMICONDUCTOR PROCESSING INTEGRATION FOR BIPOLAR JUNCTION TRANSISTOR (BJT)

#10 | 2025-03-06

US20250079415A1

Electricity

INTEGRATED CIRCUIT INCLUDING FLASH MEMORY AND CMOS LOGIC CIRCUITRY

#11 | 2025-02-06

US20250046375A1

Physics

INTEGRATED CIRCUIT INCLUDING FLASH MEMORY AND CMOS LOGIC CIRCUITRY

InventorID:

6923495 ⎘