Paul A. Bunce

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

Managing semiconductor memory array leakage current

Managing semiconductor memory array leakage current

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

Incorporating bit write capability with column interleave write enable and column redundancy steering

Write/read priority blocking scheme using parallel static address decode path

Write/read priority blocking scheme using parallel static address decode path

SRAM supply voltage global bitline precharge pulse

Cache array with reduced power consumption

Cache array with reduced power consumption

High frequency write through memory device

Increasing memory operating frequency

Port enable signal generation for gating a memory array device output

Internal bypassing of memory array devices

Split voltage level restore and evaluate clock signals for memory address decoding

Jam latch for latching memory array output data

Programmable control clock circuit including scan mode

Write control method for a memory array configured with multiple memory subarrays

CLOCK CONTROL METHOD AND APPARATUS FOR A MEMORY ARRAY

Write control circuitry and method for a memory array configured with multiple memory subarrays

Integrated system logic and ABIST data compression for an SRAM directory

Method for enabling scan of defective ram prior to repair

Circuit and method for writing a binary value to a memory cell

Programmable analog control of a bitline evaluation circuit

Method and apparatus for address generation

Method and circuit for implementing array bypass operations without access penalty

Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays

Write control circuitry and method for a memory array configured with multiple memory subarrays

Circuit for interfacing local bitlines with global bitline

Write driver circuit for memory array

Clocked preconditioning of intermediate nodes

Clock control method and apparatus for a memory array

Memory output timing control circuit with merged functions

System and method for synchronizing memory array signals

Method for skip over redundancy decode with very low overhead