John D. Davis

Managing semiconductor memory array leakage current

Managing semiconductor memory array leakage current

Incorporating bit write capability with column interleave write enable and column redundancy steering

Cache array with reduced power consumption

Cache array with reduced power consumption

High frequency write through memory device

Increasing memory operating frequency

Write control method for a memory array configured with multiple memory subarrays

Write control circuitry and method for a memory array configured with multiple memory subarrays

Method for enabling scan of defective ram prior to repair

Circuit and method for writing a binary value to a memory cell

Programmable analog control of a bitline evaluation circuit

Method and apparatus for address generation

Apparatus and method for SRAM decoding with single signal synchronization

Method and circuit for implementing array bypass operations without access penalty

Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays

Write control circuitry and method for a memory array configured with multiple memory subarrays

Circuit for interfacing local bitlines with global bitline

Write driver circuit for memory array

Clocked preconditioning of intermediate nodes

Memory output timing control circuit with merged functions

System and method for synchronizing memory array signals

Method for skip over redundancy decode with very low overhead