Jericho, Vermont
United States
28
2024-09-05
The entities that hold a legal rights for patent applications filed by inventor Porth Bruce W.:
Bruce W. Porth from Jericho, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SEMICONDUCTOR ON INSULATOR WAFER WITH CAVITY STRUCTURES
#2 | 2022-03-24Semiconductor on insulator wafer with cavity structures
#3 | 2022-03-03Wafer with localized semiconductor on insulator regions with cavity structures
#4 | 2020-06-25Semiconductor isolation structures comprising shallow trench and deep trench isolation
#5 | 2020-03-05Integrated photodetector waveguide structure with alignment tolerance
#6 | 2020-02-20Integrated photodetector waveguide structure with alignment tolerance
#7 | 2019-11-14Integrated photodetector waveguide structure with alignment tolerance
#8 | 2019-10-03Integrated photodetector waveguide structure with alignment tolerance
#9 | 2019-02-14Integrated photodetector waveguide structure with alignment tolerance
#10 | 2018-11-15Integrated photodetector waveguide structure with alignment tolerance
#11 | 2018-03-29Integrated photodetector waveguide structure with alignment tolerance
#12 | 2017-05-11Integrated photodetector waveguide structure with alignment tolerance
#13 | 2017-05-04Integrated photodetector waveguide structure with alignment tolerance
#14 | 2016-11-03Integrated photodetector waveguide structure with alignment tolerance
#15 | 2016-09-08Integrated photodetector waveguide structure with alignment tolerance
#16 | 2016-03-24Integrated photodetector waveguide structure with alignment tolerance
#17 | 2015-12-17Integrated photodetector waveguide structure with alignment tolerance
#18 | 2015-12-17Integrated photodetector waveguide structure with alignment tolerance
#19 | 2015-12-17Integrated photodetector waveguide structure with alignment tolerance
#20 | 2015-07-09Integrated photodetector waveguide structure with alignment tolerance
#21 | 2015-05-14Handle wafer
#22 | 2014-07-24FERROELECTRIC RANDOM ACCESS MEMORY WITH OPTIMIZED HARDMASK
#23 | 2014-03-27Ferroelectric random access memory with optimized hardmask
#24 | 2007-12-13METHOD FOR FABRICATING DOPED POLYSILICON LINES
#25 | 2006-12-07Deep trench formation in semiconductor device fabrication
#26 | 2006-04-20Deep trench formation in semiconductor device fabrication
#27 | 2006-04-06Method for fabricating doped polysilicon lines
#28 | 2006-03-23Chemical mechanical polishing method
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