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Inventor profile of:

Che Chen

City:

Boise, Idaho

Country:

United States

Published Applications:

7

Last publication date:

2026-06-11

Recent patent applications by Chen Che

Che Chen from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-06-11
US20260161300A1
Physics

ADJUSTING ERASE AMPLIFICATION OF A MEMORY DEVICE

#2 | 2026-05-14
US20260134935A1
Physics

METHOD FOR COLLECTING VALLEY AND PEAK INFORMATION FOR DEBUGGING A MEMORY DEVICE

#3 | 2026-05-14
US20260133699A1
Physics

READ LEVEL ADJUSTMENT FOR MEMORY DEVICE

#4 | 2026-01-22
US20260023504A1
Physics

HIGH ENDURANCE TRIM VALUES FOR NONPERFORMANCE-TYPE WRITE COMMANDS

#5 | 2025-09-04
US20250278202A1
Physics

EDGE BLOCK ASSIGNMENT TO SINGLE LEVEL CELL (SLC) MODE IN MEMORY DEVICES

#6 | 2025-06-19
US20250201311A1
Physics

REUSING PARTIALLY FILLED SUPERBLOCKS FOR PROGRAMMING

#7 | 2025-06-05
US20250181240A1
Physics

BLOCK-EFFICIENT WRITE POLICIES FOR MEMORY DEVICES

InventorID:

7039134 ⎘

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