Jericho, Vermont
United States
28
2014-03-27
The entities that hold a legal rights for patent applications filed by inventor Polson Anthony D.:
Anthony D. Polson from Jericho, US has applied for patents for these inventions. The list has both pending applications and granted patents:
On-going reliability monitoring of integrated circuit chips in the field
#2 | 2011-03-31Characterization of long range variability
#3 | 2011-02-03Detecting chip alterations with light emission
#4 | 2010-04-08Functional frequency testing of integrated circuits
#5 | 2010-04-08Functional frequency testing of integrated circuits
#6 | 2009-11-12Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells
#7 | 2009-11-12Integrated circuit with uniform polysilicon perimeter density, method and design structure
#8 | 2009-09-10Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point
#9 | 2009-08-27System and method to optimize semiconductor power by integration of physical design timing and product performance measurements
#10 | 2009-08-20IC chip design modeling using perimeter density to electrical characteristic correlation
#11 | 2009-04-21Clock-skew tuning apparatus and method
#12 | 2009-02-03Design structure for monitoring cross chip delay variation on a semiconductor device
#13 | 2008-12-18Method and system for evaluating timing in an integrated circuit
#14 | 2008-09-18High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips
#15 | 2008-09-04Slack sensitivity to parameter variation based timing analysis
#16 | 2008-08-21Method of generating wiring routes with matching delay in the presence of process variation
#17 | 2008-08-14Method of generating wiring routes with matching delay in the presence of process variation
#18 | 2008-02-28Slack sensitivity to parameter variation based timing analysis
#19 | 2007-12-06Functional frequency testing of integrated circuits
#20 | 2007-09-20System and method of analyzing timing effects of spatial distribution in circuits
#21 | 2007-03-15Method and system for performing shapes correction of a multi-cell reticle photomask design
#22 | 2007-01-04Method and structure for chip-level testing of wire delay independent of silicon delay
#23 | 2006-11-02Method of generating wiring routes with matching delay in the presence of process variation
#24 | 2006-08-31Method and system for evaluating timing in an integrated circuit
#25 | 2006-05-11Slack sensitivity to parameter variation based timing analysis
#26 | 2006-02-23Functional frequency testing of integrated circuits
#27 | 2005-11-03System and method of analyzing timing effects of spatial distribution in circuits
#28 | 2005-11-03Method and system for evaluating timing in an integrated circuit
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