Dharmendra S. Modha

MECHANISM FOR EFFICIENT MASSIVELY-CONCURRENT CONDITIONAL COMPUTATION

Runtime reconfigurable neural network processor core

AN EFFICIENT METHOD FOR VLSI IMPLEMENTATION OF USEFUL NEURAL NETWORK ACTIVATION FUNCTIONS

MODULAR NEURAL NETWORK COMPUTING APPARATUS WITH DISTRIBUTED NEURAL NETWORK STORAGE

NEURAL NETWORK ACCELERATOR OUTPUT RANKING

HORIZONTAL AND VERTICAL ASSERTIONS FOR VALIDATION OF NEUROMORPHIC HARDWARE

SYMBOLIC VALIDATION OF NEUROMORPHIC HARDWARE

CONFLICT-FREE, STALL-FREE, BROADCAST NETWORK ON CHIP

CHIPS SUPPORTING CONSTANT TIME PROGRAM CONTROL OF NESTED LOOPS

MEMORY-MAPPED NEURAL NETWORK ACCELERATOR FOR DEPLOYABLE INFERENCE SYSTEMS

Neural network weight distribution from a grid of memory elements

Learned step size quantization

COMPRESSED WEIGHT DISTRIBUTION IN NETWORKS OF NEURAL PROCESSORS

Flexible precision neural inference processing unit

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

3D NEURAL INFERENCE PROCESSING UNIT ARCHITECTURES

Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine

Performing error detection during deterministic program execution

Globally asynchronous and locally synchronous (GALS) neuromorphic network

Core utilization optimization by dividing computational blocks across cores

Massively parallel neural inference computing elements

Compound instruction set architecture for a neural inference chip

Networks for distributing parameters and data to neural network compute cores

Data representation for dynamic precision in neural network cores

Data distribution in an array of neural network cores

Fault-tolerant power-driven synthesis

Neuromorphic event-driven neural computing architecture in a scalable neural network

Extracting motion saliency features from video using a neurosynaptic system

SCHEDULER FOR MAPPING NEURAL NETWORKS ONTO AN ARRAY OF NEURAL CORES IN AN INFERENCE PROCESSING UNIT

MULTI-COMPARTMENT NEURONS WITH NEURAL CORES

Scene understanding using a neurosynaptic system

HIERARCHICAL PARALLELISM IN A NETWORK OF DISTRIBUTED NEURAL NETWORK CORES

Instruction distribution in an array of neural network cores

Scheduler and simulator for an area-efficient, reconfigurable, energy-efficient, speed-efficient neural network

Memory-mapped interface to message-passing computing systems

Runtime reconfigurable neural network processor core

Parallel computational architecture with reconfigurable core-level and vector-level parallelism

Synaptic, dendritic, somatic, and axonal plasticity in a network of neural cores using a plastic multi-stage crossbar switching

Yield tolerance in a neurosynaptic system

Unsupervised, supervised and reinforced learning via spiking computation

Neural hardware accelerator for parallel and distributed tensor computations

CENTRAL SCHEDULER AND INSTRUCTION DISPATCHER FOR A NEURAL INFERENCE PROCESSOR

TIME, SPACE, AND ENERGY EFFICIENT NEURAL INFERENCE VIA PARALLELISM AND ON-CHIP MEMORY

Massively parallel neural inference computing elements

Defect resistant designs for location-sensitive neural network processor arrays

BLOCK TRANSFER OF NEURON OUTPUT VALUES THROUGH DATA MEMORY FOR NEUROSYNAPTIC PROCESSORS

Peripheral device interconnections for neurosynaptic systems

Optimizing neurosynaptic networks

Transform for a neurosynaptic core circuit

FUNCTIONAL SYNTHESIS OF NETWORKS OF NEUROSYNAPTIC CORES ON NEUROMORPHIC SUBSTRATES

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Optimizing core utilization in neurosynaptic systems

Multi-modal neural network for universal, online learning

Hardware architecture for simulating a neural network of neurons

Scalable neural hardware for the noisy-OR model of Bayesian networks

Transform for a neurosynaptic core circuit

Hardware-software co-design of neurosynaptic systems

Memory-mapped interface for message passing computing systems

Automatic timing resolution among neural network components

Single router shared by a plurality of chip structures

Scene understanding using a neurosynaptic system

Classifying features using a neurosynaptic system

Yield tolerance in a neurosynaptic system

Scene understanding using a neurosynaptic system

Unsupervised, supervised and reinforced learning via spiking computation

Graph partitioning and placement for multi-chip neurosynaptic networks

Lens distortion correction using a neurosynaptic circuit

Lens distortion correction using a neurosynaptic circuit

Dual deterministic and stochastic neurosynaptic core circuit

Long-short term memory (LSTM) cells on spiking neuromorphic hardware

Providing transposable access to a synapse array using a recursive array layout

Compositional prototypes for scalable neurosynaptic networks

Area-efficient, reconfigurable, energy-efficient, speed-efficient neural network substrate

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Structural descriptions for neurosynaptic networks

Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm

Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array

Mapping neural dynamics of a neural model on to a coarsely grained look-up table

Extracting motion saliency features from video using a neurosynaptic system

Scaling multi-core neurosynaptic networks across chip boundaries

Lens distortion correction using a neurosynaptic circuit

Converting spike event data to digital numeric data

Converting digital numeric data to spike event data

Structural plasticity in spiking neural networks with symmetric dual of an electronic neuron

Mapping graphs onto core-based neuromorphic architectures

Lens distortion correction using a neurosynaptic circuit

Canonical spiking neuron network for spatiotemporal associative memory

Event-driven universal neural network circuit

Hierarchical scalable neuromorphic synaptronic system for synaptic and structural plasticity

Lens distortion correction using a neurosynaptic system

Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency

Extracting salient features from video using a neurosynaptic system

Transform architecture for multiple neurosynaptic core circuits

Unsupervised, supervised and reinforced learning via spiking computation

Transform for a neurosynaptic core circuit

Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs

Multi-modal neural network for universal, online learning

Multi-scale spatio-temporal neural network system

Structural descriptions for neurosynaptic networks