Inventor profile of:

David Neto

City:

Toronto

Country:

Canada

Published Applications:

18

Last publication date:

2020-03-24

Top Assignees for applications by David Neto

The entities that hold a legal rights for patent applications filed by inventor Neto David:

Recent patent applications by Neto David

David Neto from Toronto, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-03-24
US13486151
Physics

M/A for compiling parallel program having barrier synchronization for programmable hardware

#2 | 2019-09-17
US14546080
Physics

Method and apparatus for deriving signal activities for power analysis and optimization

#3 | 2017-07-04
US12563095
Physics

Metastability-hardened synchronization circuit

#4 | 2016-05-17
US14229358
Physics

Method and apparatus for protecting, optimizing, and reporting synchronizers

#5 | 2016-05-03
US13012717
Physics

Power-aware RAM processing

#6 | 2014-11-25
US11414933
-

Method and apparatus for deriving signal activities for power analysis and optimization

#7 | 2014-05-20
US12384377
-

Method and apparatus for protecting, optimizing, and reporting synchronizers

#8 | 2013-07-30
US12955521
-

Systems and methods for optimizing placement and routing

#9 | 2012-08-21
US11414803
-

Method and apparatus for deriving signal activities for power analysis and optimization

#10 | 2011-09-06
US12536298
-

Power reduction techniques for components in integrated circuits

#11 | 2011-08-16
US11294702
-

Method and apparatus for compiling programmable logic device configurations

#12 | 2011-01-25
US11510018
-

Power-aware RAM processing

#13 | 2011-01-25
US11414855
-

Method and apparatus for deriving signal activities for power analysis and optimization

#14 | 2010-08-10
US11807437
-

Method and apparatus for reducing dynamic power in a system

#15 | 2009-09-08
US11431850
-

Power reduction techniques for components in integrated circuits by assigning inputs to a plurality of ports based on power consumption ratings

#16 | 2009-06-30
US11520944
-

Computer-aided-design tools for reducing power consumption in programmable logic devices

#17 | 2009-06-09
US11550132
-

Clock distribution for specialized processing block in programmable logic device

#18 | 2005-10-18
US10298259
-

Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements

InventorID:

7137805 ⎘