Pleasanton, California
United States
36
2024-09-10
The entities that hold a legal rights for patent applications filed by inventor Keller Igor:
Igor Keller from Pleasanton, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Circuit design modification using timing-based yield calculation
#2 | 2024-05-02EFFICIENT DELAY CALCULATIONS IN REPLICATED DESIGNS
#3 | 2023-10-03Cell instance charge model for delay calculation
#4 | 2021-11-30Method, system, and product for deferred merge based method for graph based analysis pessimism reduction
#5 | 2020-09-29Characterizing electronic component parameters including on-chip variations and moments
#6 | 2019-10-01Method and apparatus for yield calculation using statistical timing data that accounts for path and stage delay correlation
#7 | 2019-04-30Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design
#8 | 2019-01-29Pseudo-inverter configuration for signal electromigration analysis
#9 | 2019-01-22Systems and methods for statistical static timing analysis
#10 | 2018-09-11Systems and methods for statistical static timing analysis
#11 | 2018-03-27System and method for accurate modeling of back-miller effect in timing analysis of digital circuits
#12 | 2018-01-30Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact
#13 | 2017-07-18Methods, systems, and articles of manufacture for enhancing timing analyses with reduced timing libraries for electronic designs
#14 | 2017-02-28Using waveform propagation for accurate delay calculation
#15 | 2016-07-05View data sharing for efficient multi-mode multi-corner timing analysis
#16 | 2015-09-08Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages
#17 | 2015-04-07Lumped aggressor model for signal integrity timing analysis
#18 | 2015-02-24Static timing analysis methods for integrated circuit designs using a multi-CCC current source model
#19 | 2015-01-20Method and apparatus for comprehension of common path pessimism during timing model extraction
#20 | 2014-12-30Constructing equivalent waveform models for static timing analysis of integrated circuit designs
#21 | 2014-07-15Waveform based variational static timing analysis
#22 | 2014-04-03Generating an equivalent waveform model in static timing analysis
#23 | 2013-12-24Methods for compact modeling of circuit stages for static timing analysis of integrated circuit designs
#24 | 2013-12-03Equivalent waveform model for static timing analysis of integrated circuit designs
#25 | 2013-11-26Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs
#26 | 2013-09-24Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs
#27 | 2013-08-20Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model
#28 | 2013-02-12Methods and apparatus for waveform based variational static timing analysis
#29 | 2012-12-25Methods and apparatus for waveform based variational static timing analysis
#30 | 2012-10-30Compact modeling of circuit stages for static timing analysis of integrated circuit designs
#31 | 2012-08-14Methods and apparatus for waveform based variational static timing analysis
#32 | 2011-02-01Timing and signal integrity analysis of integrated circuits with semiconductor process variations
#33 | 2010-07-20Method and system for crosstalk analysis
#34 | 2009-08-06Method and apparatus for thermal analysis
#35 | 2009-07-14System, method and computer program product for handling small aggressors in signal integrity analysis
#36 | 2008-12-09Method and system or generating a current source model of a gate
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