Inventor profile of:

Steven BARTLING

City:

Plano, Texas

Country:

United States

Published Applications:

17

Last publication date:

2020-03-05

Top Assignees for applications by Steven BARTLING

The entities that hold a legal rights for patent applications filed by inventor BARTLING Steven:

Recent patent applications by BARTLING Steven

Steven BARTLING from Plano, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-03-05
US20200073667A1
Physics

Electronic device and method for data processing using virtual register mode

#2 | 2015-10-29
US20150309801A1
Physics

Electronic device and method for data processing using virtual register mode

#3 | 2015-02-19
US20150048872A1
Electricity

Dual-port positive level sensitive reset data retention latch

#4 | 2015-02-12
US20150042390A1
Electricity

Dual-port positive level sensitive data retention latch

#5 | 2014-11-27
US20140347114A1
Electricity

Negative edge flip-flop with dual-port slave latch

#6 | 2014-11-27
US20140347113A1
Electricity

Positive edge flip-flop with dual-port slave latch

#7 | 2014-11-06
US20140328115A1
Electricity

Positive edge preset reset flip-flop with dual-port slave latch

#8 | 2014-08-21
US20140232443A1
Electricity

NEGATIVE EDGE PRESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH

#9 | 2014-08-21
US20140232442A1
Electricity

Negative edge reset flip-flop with dual-port slave latch

#10 | 2014-08-21
US20140232441A1
Electricity

Positive edge preset flip-flop with dual-port slave latch

#11 | 2014-08-21
US20140232440A1
Electricity

Positive edge reset flip-flop with dual-port slave latch

#12 | 2014-08-21
US20140232439A1
Electricity

Negative edge preset reset flip-flop with dual-port slave latch

#13 | 2014-08-07
US20140218091A1
Electricity

Positive edge flip-flop with dual-port slave latch

#14 | 2014-08-07
US20140218090A1
Electricity

Negative edge flip-flop with dual-port slave latch

#15 | 2014-04-17
US20140103728A1
Electricity

Single inductor multiple output discontinuous mode DC-DC converter and process

#16 | 2012-11-22
US20120297165A1
Physics

Virtual register mode by designation of dedicated register as destination operand with switch connecting execution result feedback path and turning clock off to register file

#17 | 2010-01-07
US20100002488A1
Physics

F-SRAM margin screen

InventorID:

724760 ⎘